Manufacturing fan-out wafer level packaging
AssigneeSTMicroelectronics Asia Pacific Pte Ltd
InventorYonggang Jin
Life of this patent
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Abstract
Fan-out wafer level packaging includes an integrated circuit having a top surface, a bottom surface and a bond pad defined on the top surface, and a substrate having a cavity. An adhesive layer is positioned between a top surface of the cavity and the bottom surface of the integrated circuit, and a bump is positioned proximate a top surface of the fan-out wafer level packaging, the bump spaced apart from the integrated circuit. A redistribution layer is configured to electrically couple the bond pad of the integrated circuit to the bump.
Claims19
A method of manufacturing fan-out wafer level packaging, the method comprising:
- forming a cavity in a substrate;
- forming an adhesive layer on at least a portion of a top surface of the cavity;
- placing an integrated circuit having a top surface and a bond pad on the top surface within the cavity, at least a portion of a bottom surface of the integrated circuit contacting the adhesive layer;
- forming a redistribution layer configured to electrically couple the bond pad of the integrated circuit to a redistributed bond pad;
- and
- forming a bump at the redistributed bond pad.
Fan-out wafer level packaging, comprising:
- an integrated circuit having a top surface, a bottom surface and a bond pad defined on the top surface;
- a substrate having a cavity;
- an adhesive layer positioned between a top surface of the cavity and the bottom surface of the integrated circuit;
- a bump positioned proximate a top surface of the fan-out wafer level packaging, the bump spaced apart from the integrated circuit;
- and
- a redistribution layer configured to electrically couple the bond pad of the integrated circuit to the bump.
Dependencies are inferred from the claim text.