Accessing or interconnecting integrated circuits
AssigneeCrossFire Technologies, Inc.
InventorsKevin Atkinson, Clifford H. Boler
Life of this patent
Estimating the term…
Abstract
Multiple integrated circuits (ICs) die, from different wafers, can be picked-and-placed, front-side planarized using a vacuum applied to a planarizing disk, and attached to each other or a substrate. The streets between the IC die can be filled, and certain techniques or fixtures allow application of monolithic semiconductor wafer processing for interconnecting different die. High density I/O connections between different IC die can be obtained using structures and techniques for aligning vias to I/O structures, and programmably routing IC I/O lines to appropriate vias. Existing IC die can be retrofitted for such interconnection to other IC die, such as by using similar techniques or tools.
Claims29
An apparatus comprising:
- laterally attached first and second integrated circuit die;
- and
- a monolithic first insulator layer extending over the first and second integrated circuit die, a first via extending over and electrically connecting to a plurality of conductive input/output structures on the first integrated circuit that are configured to respectively carry distinct signals, and wherein the first integrated circuit includes a programming circuit to select which of the plurality of conductive input/output structures under the first via on the first integrated circuit electrically conductively communicates with the second integrated circuit using the first via.
A method comprising:
- positioning and actively drawing front sides of respective first and second integrated circuit die against a shared planarizing surface and holding the front sides in substantially planar alignment, wherein the front sides comprise circuitry formed therein;
- laterally attaching the respective first and second integrated circuit die to each other, such that the front sides remain in substantially planar alignment, including filling a street between the first and second integrated circuit die substantially without also continuously filling regions under back sides of the first and second integrated circuit die;
- forming a monolithic first insulator overlying the first and second integrated circuit die while the first and second integrated circuit die are substantially laterally attached to each other by the filled streets;
- forming a first via over the first integrated circuit die;
- forming a second via over the second integrated circuit die;
- and
- electrically interconnecting the first and second integrated circuit die by forming a conductor therebetween, including electrically interconnecting the first and second vias.
Dependencies are inferred from the claim text.