Quad flat non-leaded package and manufacturing method thereof
AssigneeAdvanced Semiconductor Engineering, Inc.
InventorMing-Chiang Lee
Life of this patent
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Abstract
A quad flat non-leaded package including a first patterned conductive layer, a second patterned conductive layer, a chip, bonding wires and a molding compound is provided. The first patterned conductive layer defines a first space, and the second patterned conductive layer defines a second space, wherein the first space overlaps the second space and a part of the second patterned conductive layer surrounding the second space. The chip is disposed on the second patterned conductive layer. The bonding wires are connected between the chip and the second patterned conductive layer. The molding compound encapsulates the second patterned conductive layers, the chip and the bonding wires. In addition, a method of manufacturing a quad flat non-leaded package is also provided.
Claims20
A quad flat non-leaded package, comprising:
- a first patterned conductive layer, defining a first space having a pattern complementary to a pattern of the first patterned conductive layer;
- a second patterned conductive layer, defining a second space having a pattern complementary to a pattern of the second patterned conductive layer, wherein the first space overlaps the second space and a part of the second patterned conductive layer surrounding the second space;
- a chip, disposed on the second patterned conductive layer, wherein the second patterned conductive layer is located between the chip and the first patterned conductive layer;
- a plurality of bonding wires, connected between the chip and the second patterned conductive layer;
- and
- a molding compound, encapsulating the second patterned conductive layer, the chip and the bonding wires.
A method of manufacturing a quad flat non-leaded package, the method comprising:
- providing a sacrificed layer, two release films and two metal layers;
- stacking the sacrificed layer between the two release films and stacking the two release films and the sacrificed layer between the two metal layers, wherein each release film exposes a part of the sacrificed layer, and each metal layer covers one of the release films and the part of the sacrificed layer exposed by the release film;
- forming a first mask layer on each metal layer, wherein each first mask layer exposes a part of the corresponding metal layer;
- forming a first patterned conductive layer on the part of the metal layer exposed by each first mask layer;
- removing each first mask layer and each first patterned conductive layer exposes a part of the corresponding metal layer;
- forming a dielectric layer on the part of the corresponding metal layer exposed by each first patterned conductive layer;
- cutting the dielectric layers, the metal layers, the release films and the sacrificed layer;
- removing the sacrificed layer and the release films after cutting the dielectric layers, the metal layers, the release films and the sacrificed layer;
- removing the metal layers after removing the sacrificed layer and the release films;
- disposing at least one chip on each first patterned conductive layer;
- and
- forming a plurality of bonding wires to electrically connect each chip to the corresponding first patterned conductive layer.
A method of manufacturing a quad flat non-leaded package, the method comprising:
- providing a sacrificed layer, two release films and two metal layers;
- stacking the sacrificed layer between the two release films and stacking the two release films and the sacrificed layer between the two metal layers, wherein each release film exposes a part of the sacrificed layer, and each metal layer covers one of the release films and the part of the sacrificed layer exposed by the release film;
- forming a first mask layer on each metal layer, wherein each first mask layer exposes a part of the corresponding metal layer;
- forming a first patterned conductive layer on the part of the metal layer exposed by each first mask layer;
- cutting the dielectric layers, the metal layers, the release films and the sacrificed layer;
- removing the sacrificed layer and the release films after cutting the dielectric layers, the metal layers, the release films and the sacrificed layer;
- removing the metal layers after removing the sacrificed layer and the release films;
- disposing at least one chip on each first patterned conductive layer;
- forming a plurality of bonding wires to electrically connect each chip to the corresponding first patterned conductive layer;
- forming a plurality of molding compounds, wherein each molding compound encapsulates the corresponding chip and the bonding wires connected to the chip;
- and
- removing the first mask layers.
Dependencies are inferred from the claim text.