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US 2010/0140777 A1Published application
Stacked ball grid array package module utilizing one or more interposer layers
AssigneeAprolase Development Co., LLC
InventorsDaniel Michaels, William E. Boyd
Life of this patent
Estimating the term…
Abstract
A multilayer module comprised of stacked IC package layers is disclosed. A plurality of layers preferably having ball grid array I/O are stacked and interconnected using one or more interposer layers for the routing of electronic signals to appropriate locations in the module through angularly depending leads. The stack is further comprised of an interface PCB for the routing of electronics signals to and from the layers in the module and for connection to an external circuit.
Claims21
-11. (canceled)
An electronic module comprising:
- a first integrated circuit (IC) package layer including a first input/output (I/O) pad;
- an interposer layer including a lead that comprises a terminal configured to route an electrical signal to the first I/O pad;
- a second IC package layer including a second I/O pad;
- and
- an interface printed circuit board (PCB) including:
- a plurality of third I/O pads;
- and
- a plurality of interface PCB conductive traces configured to route electrical signals among the first, second, and plurality of third I/O pads, wherein one of the plurality of interface PCB conductive traces terminates at or is adjacent to a peripheral surface of the interface PCB to define an interface PCB connection point;
- wherein the lead is angularly disposed with respect to the interposer layer to couple to the interface PCB connection point.
6 more elements
An electronic module comprising:
- a first integrated circuit (IC) package layer including a first plurality of input/output (I/O) pads;
- an interposer layer including:
- a plurality of interposer conductive pads;
- and
- a plurality of leads, each lead comprising a terminal, wherein the plurality of leads are disposed at an angle with respect to the interposer layer;
- wherein one of the plurality of interposer conductive pads is electrically connected to one of the first plurality of I/O pads and one of the terminals and is configured to route an electrical signal therebetween;
- a second IC package layer including a second plurality of I/O pads;
- and
- an interface printed circuit board (PCB) including:
- a plurality of interface PCB conductive pads;
- a third plurality of I/O pads;
- and
- a plurality of interface PCB connection points;
- wherein one of the plurality of interface PCB connection points is electrically connected to one of the terminals and configured to route an electrical signal to one of the first plurality of I/O pads;
- wherein the interface PCB further includes a plurality of interface PCB conductive traces configured to route electrical signals from the third plurality of I/O pads to predefined ones of the terminals and predefined ones of the second plurality of I/O pads.
12 more elements
A system comprising:
- a plurality of integrated circuit (IC) package layers, each IC package layer including a plurality of input/output (I/O) pads;
- an interposer layer disposed between two of the plurality of IC package layers, wherein the interposer layer includes:
- a plurality of interposer conductive pads;
- and
- a plurality of leads, each lead comprising a terminal, wherein the plurality of leads are disposed at an angle with respect to the interposer layer;
- wherein one of the plurality of interposer conductive pads is electrically connected to one of the plurality of I/O pads and one of the terminals and is configured to route an electrical signal therebetween;
- and
- an interface printed circuit board (PCB) including:
- a plurality of interface PCB conductive pads;
- and
- a castellation connection point located on a peripheral surface of the interface PCB;
- wherein the castellation connection point is electrically connected to one of the terminals and configured to route an electrical signal to one of the plurality of I/O pads;
- wherein the interface PCB further includes a plurality of interface PCB conductive traces configured to route electrical signals among the plurality of I/O pads and the terminals.
10 more elements
Dependencies are inferred from the claim text.