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US 2010/0140776 A1Published application
Triaxial through-chip connecton
AssigneeCufer Asset Ltd. L.L.C.
InventorJohn Trezza
Life of this patent
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Abstract
A method performed on a wafer having multiple chips each including a doped semiconductor and substrate involves etching an annulus trench, metalizing an inner and an outer perimeter side wall of the annulus trench, etching a via trench into the wafer, making a length of the via trench electrically conductive, thinning a surface of the substrate.
Claims37
An integrated circuit chip comprising:
- a semiconductor;
- a substrate located adjacent to the semiconductor;
- an annular trench extending into the semiconductor and the substrate, wherein the annular trench includes an insulating material;
- a first electrically conductive material bounding at least a portion of an outer surface of the insulating material;
- a second electrically conductive material bounding at least a portion of an inner surface of the insulating material;
- and
- a third electrically conductive material surrounded by the inner surface of the insulating material;
- wherein the first, second, and third electrically conductive materials are electrically isolated from each other.
5 more elements
An integrated circuit chip comprising:
- a semiconductor material;
- a via extending into the semiconductor material, wherein the via includes an annulus of insulating material;
- a first electrically conductive material bounding at least a portion of an outer surface of the annulus of insulating material;
- a second electrically conductive material bounding at least a portion of an inner surface of the annulus of insulating material;
- and
- a third electrically conductive material within the annulus of insulating material;
- wherein the first, second, and third electrically conductive materials are electrically isolated from each other.
4 more elements
A stack of integrated circuit chips comprising:
- a first chip, wherein the first chip includes:
- a semiconductor;
- a via extending into the semiconductor, wherein the via includes an annulus of insulating material;
- a first electrically conductive material bounding at least a portion of an outer surface of the annulus of insulating material;
- a second electrically conductive material bounding at least a portion of an inner surface of the annulus of insulating material;
- and
- a third electrically conductive material within the annulus of insulating material;
- wherein the first, second, and third electrically conductive materials are electrically isolated from each other;
- and
- a second chip, wherein the second chip includes a first electrical contact that is electrically connected to at least one of the first, second, or third electrically conductive materials.
7 more elements
An electronic device comprising a chip, wherein the chip includes a doped semiconductor and a substrate and is processed by a method comprising:
- etching a via trench between an outer surface of the doped semiconductor and the substrate, wherein a first portion of the via trench is bounded by the doped semiconductor and a second portion of the via trench is bounded by the substrate;
- coating at least a portion of an outer wall of the via trench with a first electrically conductive material;
- coating at least a portion of an inner wall of the via trench with a second electrically conductive material;
- introducing a third electrically conductive material in the via trench to form an electrically conductive path between the doped semiconductor and the substrate;
- and
- thinning a surface of the substrate to expose the first, second, and third electrically conductive materials, wherein the first, second, and third electrically conductive materials are electrically isolated from each other.
3 more elements
Dependencies are inferred from the claim text.