Parallel Plane Memory and Processor Coupling in a 3-D Micro-Architectural System
AssigneeQUALCOMM Incorporated
InventorThomas R. Toms
Life of this patent
Estimating the term…
Abstract
An IC device is constructed in a manner that allows for the memory and processor elements to be positioned one above the other on parallel planes of a 3-D structure. Interconnections between the memory(s) and the processor(s) are accomplished by using through substrate stacking (TSS) techniques. This arrangement provides the processor with direct access to the memory by reducing the distance between the memory and the processor.
Claims21
An IC device comprising:
- a first tier having constructed therein a first portion of a micro architecture;
- a second tier having constructed therein a second portion of said micro architecture, said first and second portions requiring close communication;
- and
- a series of connections enabling communication between said first and second portions.
A method for constructing an IC device, said method comprising:
- constructing a first tier having therein a first portion of a micro architecture;
- constructing a second tier having therein a second portion of said micro architecture, said first and second portions requiring close communication;
- coupling said second tier to said first tier;
- and
- constructing a series of vias through at least one of said tiers to allow for communication between said first and second portions.
An IC device comprising:
- a first tier having constructed therein memory elements along a plane of said tier;
- a second tier stacked with said first tier within said IC device, said second tier having constructed therein a micro-processor relying on close coupling with said memory elements for operation;
- and
- a series of connections distributed about said plane of said first tier, said connections enabling said close coupling.
A method for constructing an IC device, said method comprising:
- constructing a first tier of said IC device using a first process, said first process compatible with creation within said first tier of a first set of elements;
- constructing a second tier of said IC device using a second process, said second process compatible with creation within said second tier of a second set of elements in a same pipeline stage as said first set of elements;
- and
- bonding said first and second tiers together to form at least a portion of said IC device, said bonding facilitating close-coupled communication between certain of said first and second element sets, wherein one of said element sets are memories and the other of said element sets are devices which require close coupling with said memory.
A method for constructing an IC device, said method comprising:
- constructing a first semi-conductor tier having therein a first set of elements of a pipeline stage;
- constructing a second semi-conductor tier having therein a second set of elements of the pipeline stage, and
- bonding said first and second semi-conductors together to form at least a portion of said IC device, said bonding facilitating close-coupled communication between certain of said first and second element sets which require close coupling.
Dependencies are inferred from the claim text.