# US 2010/0140749 A1 · Semiconductor device

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- Number: US 2010/0140749 A1
- Document ID: US20100140749A1
- Status: Published application
- Kind: A1
- Application number: 12/330,455
- Filed: 2008-12-08
- Published: 2010-06-10
- Earliest claimed: 2008-12-08
- Assignees: United Microelectronics Corp.
- Inventors: Chien-Li Kuo
- Web page: https://patentgrep.com/patent/US20100140749A1

## CPC

- H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
- H10W 20/0238: {comprising etching via holes through pads or through electrodes}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 90/00: Package configurations
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/922: {Bond pads being integral with underlying chip-level interconnections}
- H10W 72/9223: {with redistribution layers [RDL]}
- H10W 72/9226: {with via interconnections}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device with a TSV and a shelter is provided. The semiconductor device includes a substrate, a circuit area, at least a TSV and a shelter. The circuit area and the TSV are disposed on the substrate, and the TSV penetrates through the substrate. The shelter is disposed on the substrate and at least one part thereof is between the circuit area and the TSV in order to shelter EMI between the TSV and the circuit area. The novel structure prevents the circuits in the circuit area being affected by noise caused by TSV when TSV acts as a power pin.

## Claims

### Claim 1

A semiconductor device comprises:
a substrate;
a circuit area;
at least a TSV that penetrates through the substrate; and
a first shelter disposed on the substrate and at least a part of the first shelter is between the TSV and the circuit area.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising a power input/output pad disposed on the substrate, wherein the TSV is electrically coupled to the power input/output pad.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, further comprising a plurality of metal interconnect layers, wherein the metal interconnect layers comprise:
a first metal interconnect layer that includes the first shelter; and
a second metal interconnect layer that includes a connecting circuit;
wherein the connecting circuit is electrically coupled to the TSV and the power input/output pad.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein the first shelter is disposed on the periphery of the connecting circuit.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the first shelter comprises at least a polygon metal layer.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the first shelter comprises at least an octagonal metal layer.

### Claim 7 (depends on 5)

The semiconductor device of claim 5, wherein the first shelter comprises at least a circular metal layer.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the first shelter comprises at least a continuous metal layer.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the first shelter comprises at least a dispersed metal layer.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, further comprising at least a second shelter, wherein each of the second shelters compasses the first shelter.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein at least one of the second shelters comprises a polygon metal layer.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein at least one of the second shelters comprises an octagonal metal layer.

### Claim 13 (depends on 11)

The semiconductor device of claim 11, wherein at least one of the second shelters comprise a circular metal layer.

### Claim 14 (depends on 10)

The semiconductor device of claim 10, wherein at least one of the second shelters comprise a continuous metal layer.

### Claim 15 (depends on 10)

The semiconductor device of claim 10, wherein at least one of the second shelters comprise a dispersed metal layer.

### Claim 16 (depends on 1)

The semiconductor device of claim 1, wherein the first shelter is selected from a group consisting of copper, aluminum, tungsten, titanium, titanium nitride, tantalum, tantalum nitride.

### Claim 17 (depends on 10)

The semiconductor device of claim 10, wherein the second shelter is selected from a group consisting of copper, aluminum, tungsten, titanium, titanium nitride, tantalum, tantalum nitride.

### Claim 18 (depends on 1)

The semiconductor device of claim 1, wherein the TSV is electrically coupled to a power supply.

### Claim 19 (depends on 1)

The semiconductor device of claim 1, wherein the first shelter is coupled to a ground connection.

### Claim 20 (depends on 10)

The semiconductor device of claim 10, wherein the second shelter is coupled to a ground connection.