Semiconductor device
AssigneeNEC Electronics Corporation
InventorKoujirou Matsui
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Abstract
A semiconductor device includes: a first capacitor including an upper electrode, a lower electrode, an intermediate electrode arranged between the upper electrode and the lower electrode, and a shield line arranged in the same layer as the intermediate electrode; and a second capacitor, including an upper electrode, a lower electrode, and an intermediate electrode arranged between the upper electrode and the lower electrode, and arranged adjoining to the first capacitor. In the first capacitor and the second capacitor, the upper electrode, the lower electrode and the shield line are electrically connected to a ground electrode. The shield line lies between the first capacitor and the second capacitor. Accordingly, a MIM capacitor with excellent layout efficiency is provided while noise effects are reduced.
Claims14
A semiconductor device comprising:
- a first capacitor including a first upper electrode, a first lower electrode, a first intermediate electrode arranged between the first upper electrode and the first lower electrode, and a first shield line in the same layer as the first intermediate electrode;
- and
- a second capacitor, including a second upper electrode, a second lower electrode and a second intermediate electrode arranged between the second upper electrode and the second lower electrode, and arranged adjoining to the first capacitor,
- wherein in the first capacitor and the second capacitor, the first upper electrode, the first lower electrode, the first shield line, the second upper electrode and the second lower electrode are electrically connected to a ground electrode, and
- the first shield line is arranged between the first capacitor and the second capacitor.
A semiconductor device comprising:
- a capacitor unit structure including an upper electrode, a lower electrode, an intermediate electrode arranged between the upper electrode and the lower electrode, a shield line formed in the same layer as the intermediate electrode and connected to a ground electrode, and an intermediate electrode withdrawing line formed in the same layer as the intermediate electrode and connected to the intermediate electrodes;
- and
- a capacitor sequence in which two or more said capacitor unit structures are arrayed in a row, and the intermediate electrode withdrawing lines of adjoining capacitors are connected to each other, and the shield lines of adjoining capacitors are connected to each other,
- wherein two or more said capacitor sequences are arranged adjoining to each other.
Dependencies are inferred from the claim text.