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US 2010/0140722 A1Published application
Strained Semiconductor Device and Method of Making Same
AssigneeInfineon Technologies AG
InventorRichard Lindsay
Life of this patent
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Abstract
To form a semiconductor device, an electrode layer is formed over a semiconductor body. The electrode layer includes an amorphous portion. A liner, e.g., a stress-inducing liner, is deposited over the electrode layer. The electrode layer is annealed to recrystallize the amorphous portion of the electrode layer. The liner can then be removed and an electronic component (e.g., a transistor) that includes a feature (e.g., a gate) formed from the electrode layer can be formed.
Claims20
A semiconductor device comprising:
- a channel region disposed in a semiconductor body;
- a gate dielectric overlying the channel region;
- a stressed gate electrode overlying the gate dielectric, the stressed gate electrode comprising a re-crystallized zone of a gate material disposed between at least two non re-crystallized zones of the gate material;
- a source region disposed in the semiconductor body;
- and
- a drain region disposed in the semiconductor body and spaced from the source region by the channel region.
3 more elements
A semiconductor structure comprising:
- a first isolation region and a second isolation region disposed in a semiconductor body;
- a semiconductor region disposed between the first and the second isolation regions within the semiconductor body;
- a gate dielectric layer disposed over the semiconductor body;
- a gate electrode layer disposed over the gate dielectric layer, the gate electrode layer including an amorphous portion and a crystalline portion, the amorphous portion being disposed over a first portion of the semiconductor region, the crystalline portion being disposed over a second portion and a third portion of the semiconductor region, wherein the first portion is disposed between the second and the third portions;
- and
- a stress liner disposed over the electrode layer.
3 more elements
A semiconductor structure comprising:
- isolation regions disposed in a semiconductor body;
- an active area disposed between the isolation regions within the semiconductor body;
- a gate dielectric layer disposed over the semiconductor body;
- a polysilicon layer having a top surface and an opposite bottom surface, the bottom surface of the polysilicon layer disposed on the gate dielectric layer, the polysilicon layer comprising an amorphous implanted region adjacent the top surface, the amorphous implanted region being surrounded by a crystalline region;
- and
- a stress liner disposed over the electrode layer.
3 more elements
Dependencies are inferred from the claim text.