N/P METAL CRYSTAL ORIENTATION FOR HIGH-K METAL GATE Vt MODULATION

An integrated circuit, comprising:

• a silicon substrate having a first region and a second region;
• an n-type field-effect transistor (FET) disposed in the first region, including:
• a first source and a first drain formed in the silicon substrate;
• a first gate stack interposed between the first source and first drain, the first gate stack including a high k dielectric layer, a first crystalline metal layer having a {100} orientation on the high k dielectric layer, and a conductive metal material layer on the first crystalline metal layer;
• and
• a p-type FET disposed in the second region, including:
• a second source and a second drain formed in the silicon substrate;
• a second gate stack interposed between the second source and second drain, the second gate stack including the high k dielectric layer, a second crystalline metal layer having a {111} orientation on the high k dielectric layer, and the conductive metal material layer on the second crystalline metal layer.

An integrated circuit, comprising:

• a semiconductor substrate having a first region and a second region;
• an n-type field-effect transistor (FET) in the first region, the n-type FET having a first gate stack that includes:
• a high k dielectric layer disposed over the semiconductor substrate;
• a tantalum layer disposed over the high k dielectric layer, wherein the tantalum layer has a {100} orientation interfacing the high k dielectric layer;
• and
• a conductive metal material layer on the first crystalline metal layer;
• and
• a p-type FET in the second region, the p-type FET having a second gate stack that includes:
• the high k dielectric layer disposed over the semiconductor substrate;
• a platinum layer disposed over the high k dielectric material layer, wherein the platinum layer has a {111} orientation interfacing the high k dielectric layer;
• and
• the conductive metal material layer on the second crystalline metal layer.