Semiconductor device and manufacturing method of the same

A manufacturing method of a semiconductor device comprising:

• forming a first gate electrode of a first field-effect transistor on a front surface of a silicon layer to be a memory element part of an SOI substrate in which a substrate, an insulator layer, and the silicon layer are stacked via a first gate insulating film;
• forming a first insulating film covering the first gate electrode on the front surface of the silicon layer, and further forming a support substrate on the first insulating film;
• removing the substrate and the insulator layer to expose a rear surface of the silicon layer;
• forming an element isolation region for isolation of the memory element part and a logic element part in the silicon layer;
• forming a second gate electrode of a second field-effect transistor in a location facing the first gate electrode on the rear surface of the silicon layer to be the memory element part via a second gate insulating film, and forming a third gate electrode of a third field-effect transistor on the rear surface of the silicon layer to be the logic element part via a third gate insulating film;
• forming a first source and drain region as a source and drain region in common between the first field-effect transistor and the second field-effect transistor in the silicon layer at both sides of the first gate electrode and the second gate electrode, and forming a third source and drain region of the third field-effect transistor in the silicon layer at both sides of the third gate electrode;
• forming a contact portion connecting the first gate electrode and the second gate electrode in the element isolation region;
• and
• forming a second insulating film covering the second gate electrode and the third gate electrode on the rear surface of the silicon layer,
• wherein the first field-effect transistor and the second field-effect transistor are formed to be fully-depleted field-effect transistors.

A manufacturing method of a semiconductor device comprising:

• forming an element insulation region for isolation of a memory element part and a logic element part in a silicon layer of an SOI substrate in which a substrate, an insulator layer, and the silicon layer are stacked;
• forming a second gate electrode of a second field-effect transistor on a front surface of the silicon layer to be the memory element part via a second gate insulating film, and forming a third gate electrode of a third field-effect transistor on a front surface of the silicon layer to be the logic element part;
• forming a second source and drain region of the second field-effect transistor in the silicon layer at both sides of the second gate electrode, and forming a third source and drain region of the third field-effect transistor in the silicon layer at both sides of the third gate electrode;
• forming a second insulating film covering the second gate electrode and the third gate electrode on the front surface of the silicon layer, and further forming a support substrate on the second insulating film;
• removing the substrate and the insulator layer to expose a rear surface of the silicon layer;
• forming a first gate electrode of a first field-effect transistor in a location facing the second gate electrode on the rear surface of the silicon layer to be the memory element part via a first gate insulating film;
• forming a contact portion connecting the first gate electrode and the second gate electrode in the element isolation region;
• forming a first insulating film covering the first gate electrode on the rear surface side of the silicon layer,
• wherein the first field-effect transistor and the second field-effect transistor are formed to be fully-depleted field-effect transistors.