# US 2010/0140692 A1 · Methods of fabricating semiconductor devices having multiple channel transistors and semiconductor devices fabricated thereby

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- Number: US 2010/0140692 A1
- Document ID: US20100140692A1
- Status: Published application
- Kind: A1
- Application number: 12/705,011
- Filed: 2010-02-12
- Published: 2010-06-10
- Earliest claimed: 2005-11-04
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Se-Myeong Jang; Makoto Yoshida; Jae-Rok Kahng; Hyun-Ju Sung; Hui-Jung Kim; Chang-Hoon Jeon
- Web page: https://patentgrep.com/patent/US20100140692A1

## CPC

- H10B 12/09: {with simultaneous manufacture of the peripheral circuit region and memory cells}
- H10B 63/10: Phase change RAM [PCRAM, PRAM] devices
- H10B 12/50: {Peripheral circuit region structures}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

In methods of fabricating a semiconductor device having multiple channel transistors and semiconductor devices fabricated thereby, the semiconductor device includes an isolation region disposed within a semiconductor substrate and defining a first region. A plurality of semiconductor pillars self-aligned with the first region and spaced apart from each other are disposed within the first region, and each of the semiconductor pillars has at least one recessed region therein. At least one gate structure may be disposed across the recessed regions, which crosses the semiconductor pillars and extends onto the isolation region.

## Claims

### Claim 1

A semiconductor device having a multiple channel transistor comprising:
a semiconductor substrate having a first and second isolation regions, the first and second isolation regions defining an active region;
a first semiconductor pillar having sidewalls in the active region, a portion of the sidewalls of the first semiconductor pillar in contact with the first isolation region;
second and third semiconductor pillars in the active regions, the second and third semiconductor pillars being spaced apart from the first semiconductor pillar respectively;
a first recessed region between the first and second semiconductor pillars;
a second recessed region between the second and third semiconductor pillars;
a buffer insulating layer pattern in the second recessed region;
a gate dielectric layer on the surface of the first semiconductor pillars, the second semiconductor pillars, the third semiconductor pillars, the first recessed region, and the buffer insulating layer pattern; and
a gate electrode on the gate dielectric layer.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the gate dielectric layer on the buffer insulating layer pattern has a thickness that is less than that of other portions.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, further comprising a fourth semiconductor pillar, the fourth semiconductor pillar in contact with the second isolation region and spaced apart from the third semiconductor pillar.

### Claim 4 (depends on 3)

The semiconductor device according to claim 3, further comprising at least one more semiconductor pillars between the third and fourth semiconductor pillars.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein the top portion of the buffer insulating layer pattern is at a same level as that of the top surface of the first, second, and third semiconductor pillars.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein the top portions of the first, second, and third semiconductor pillars are at a level that is higher than the top surface of the first and second isolation regions.

### Claim 7 (depends on 6)

The semiconductor device according to claim 6, wherein the bottom portions of the first and second recessed regions are at a level that is substantially the same as that of the top of the first and second isolation regions.

### Claim 8 (depends on 1)

The semiconductor device according to claim 1, wherein the top portions of the first, second, and third semiconductor pillars are at a level that is substantially the same as that of the top of the first and second isolation regions.

### Claim 9 (depends on 1)

The semiconductor device according to claim 1, wherein the bottom portion of the buffer insulating layer pattern are at a level that is substantially the same as that of the bottom of the first recessed region.

### Claim 10

A semiconductor device having a multiple channel transistor comprising:
a semiconductor substrate having a first and second isolation regions, the first and second isolation regions defining an active region;
a first semiconductor pillar having sidewalls in the active region, a portion of the sidewalls of the first semiconductor pillar in contact with the first isolation region;
second and third semiconductor pillars in the active regions, the second and third semiconductor pillars being spaced apart from the first semiconductor pillar respectively;
a first recessed region between the first and second semiconductor pillars;
a second recessed region between the second and third semiconductor pillars;
a first buffer insulating layer pattern in the first recessed region;
a second buffer insulating layer pattern in the second recessed region;
a gate dielectric layer on the surface of the first semiconductor pillars, the second semiconductor pillars, the third semiconductor pillars, the first buffer insulating layer pattern, and the second buffer insulating layer pattern; and
a gate electrode on the gate dielectric layer.

### Claim 11 (depends on 10)

The semiconductor device according to claim 10, wherein the top portions of the first and second buffer insulating layer pattern are at a level that is lower than the top of the first, second, and third semiconductor pillars.

### Claim 12 (depends on 11)

The semiconductor device according to claim 11, wherein the bottom portions of the first and second buffer insulating layer pattern are at a level that is substantially the same as that of the bottom of the first and second isolation regions.