Flash memory and method of manufacturing a flash memory
AssigneeKabushiki Kaisha Toshiba
InventorDaisuke Arizono
Life of this patent
Estimating the term…
Abstract
A semiconductor memory which includes a semiconductor substrate, a plurality of memory cells, and a plurality of active regions disposed in the substrate between adjacent ones of the memory cells. At least two contact electrodes are disposed between adjacent ones of the memory cells and each being connected to one of the active regions, and a contact member is connected to one of the contact electrodes and extending over a gate electrode of a memory cell disposed adjacent to the one contact electrode. Faults can be detected in the memory cells due to particles located between the various insulator and electrode layers in the gate electrode structure, or between the substrate and the gate insulator of the memory cell.
Claims23
A semiconductor memory comprising:
- a semiconductor substrate;
- a plurality of memory cells arranged in a first direction, the memory cell having a first insulating layer disposed on the substrate, a first gate electrode disposed over the insulating layer, and a second insulating layer disposed over upper and side surfaces of the gate electrode;
- a plurality of active regions disposed in the substrate between adjacent ones of the memory cells;
- at least two contact electrodes each being disposed between adjacent ones of the memory cells and each being connected to one of the active regions;
- and
- a contact member connected to one of the contact electrodes and extending over a gate electrode of a memory cell disposed adjacent to the one contact electrode, the contact member connected a top surface of the second insulating layer.
A method of forming a semiconductor memory, comprising:
- forming memory cells each having a gate insulator disposed on a semiconductor substrate, a gate electrode disposed over the gate insulator, and active regions formed in the substrate between the gate electrodes;
- forming first and second contact structures each being between adjacent memory cells and connected to one of the active regions;
- forming an insulating layer over the top and side surfaces of the gate electrodes;
- and
- forming a contact member connected to one of the contact structures and extending over a gate electrode of a memory cell adjacent to the one contact structure, the contact member connected a top surface of the second insulating layer.
Dependencies are inferred from the claim text.