Stacked dual-gate nmos devices with antimony source-drain regions and methods for manufacturing thereof

Abstract

A three-dimensional memory structure includes multiple layers of memory devices, each memory device including a dual-gate device. A dual-gate device includes an active layer between a first gate structure and a second gate structure. Each gate structure is isolated from the active layer by a dielectric layer and is located above a semiconductor or channel region in the active layer defined by spaced-apart diffusion regions formed by implanting antimony ions. The antimony-doped diffusion regions are particularly suitable in stacked memory devices because antimony can be implanted and activated at a temperature less than 900° C. and show little movement of the implanted antimony ions even after numerous thermal steps in the manufacturing process. As a result, dual-gate devices in a stacked memory device with well-controlled channel lengths may be achieved.

Dependencies are inferred from the claim text.