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US 2010/0140620 A1Published application
Flat-panel display semiconductor process for efficient manufacturing
AssigneePalo Alto Research Center Incorporated
InventorsJackson H. Ho, Jeng Ping Lu
Life of this patent
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Abstract
An embodiment is a method and apparatus to fabricate a flat panel display. A poly-last structure is formed for a display panel using an amorphous silicon or amorphous silicon compatible process. The poly-last structure has a channel silicon precursor. The display panel is formed from the poly-last structure using a polysilicon specific or polysilicon compatible process.
Claims24
A method comprising:
- forming a poly-last structure for a display panel using an amorphous silicon or amorphous silicon compatible process, the poly-last structure having a channel silicon precursor;
- and
- forming the display panel from the poly-last structure using a polysilicon specific or polysilicon compatible process.
A method comprising:
- forming gate, source, and drain regions on a substrate for a display panel using an amorphous silicon or amorphous silicon compatible process, the gate region corresponding to a bottom gate configuration;
- depositing a channel silicon precursor on the gate, source and drain regions in the amorphous silicon or amorphous silicon compatible process;
- and
- irradiating the channel silicon precursor by a laser using a polycrystalline silicon or polycrystalline silicon compatible process.
1 more element
A structure comprising:
- a substrate;
- a bottom gate deposited on the substrate;
- a dielectric layer deposited on the bottom gate;
- doped source and drain regions deposited on the substrate and formed around the bottom gate;
- and
- a channel silicon precursor layer deposited on the patterned doped amorphous silicon layer and the dielectric layer.
3 more elements
A display panel comprising:
- a glass substrate;
- and
- a thin film transistor (TFT) array having a plurality of TFTs as pixel switching devices on the glass substrate, each of the TFTs having a bottom gate structure with polycrystalline silicon and data interconnecting lines, the bottom gate structure and the data interconnecting lines being under a silicon layer.
Dependencies are inferred from the claim text.