Semiconductor apparatus, solid state image pickup device using the same, and method of manufacturing them
AssigneeCanon Kabushiki Kaisha
InventorTakeshi Ichikawa
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AssigneeCanon Kabushiki Kaisha
InventorTakeshi Ichikawa
Estimating the term…
The invention provides a semiconductor apparatus provided with at least one set of buried channel type first conductive type MOS transistor and surface channel type first conductive type MOS transistor on the same substrate, in which a first conductive type impurity region is provided below a gate electrode of the buried channel type and surface channel type MOS transistors and between source drain regions. Further, the invention provides a solid state image pickup device having a photoelectric conversion portion and a pixel including a plurality of transistors formed in correspondence to the photoelectric conversion portion, in a substrate, wherein the plurality of transistors includes a buried channel type first conductive type MOS transistor and a surface channel type first conductive type MOS transistor, and a first conductive type impurity region is provided below a gate electrode of the buried channel type and surface channel type MOS transistors and between source drain regions.
A semiconductor apparatus provided with at least one set of buried channel type first conductive type MOS transistor and surface channel type first conductive type MOS transistor on the same substrate, wherein a first conductive type impurity region is provided below a gate electrode of said buried channel type and surface channel type MOS transistors and between source and drain regions.
A solid state image pickup device comprising a pixel having a photoelectric conversion portion and a plurality of transistors formed in correspondence to said photoelectric conversion portion, on a substrate, wherein said plurality of transistors include a buried channel type first conductive type MOS transistor and a surface channel type first conductive type MOS transistor, and a first conductive type impurity region is provided below a gate electrode and between source and drain regions of said buried channel type and surface channel type MOS transistors.
Dependencies are inferred from the claim text.