Printed circuit board having plating pattern buried in via and method of manufacturing the same
AssigneeSamsung Electro-Mechanics Co., Ltd.
InventorsSeok Hwan Ahn, Young Gwan Ko
Life of this patent
Estimating the term…
Abstract
Disclosed is a printed circuit board having a plating pattern buried in a via and a method of manufacturing the same. The method of manufacturing the printed circuit board includes forming a negative pattern for forming a plating pattern, thus remarkably reducing the generation of plating thickness deviation in a plating process for forming a circuit pattern, and the printed circuit board has improved electrical signal transmission properties.
Claims12
A method of manufacturing a printed circuit board having a plating pattern buried in a via, comprising:
- providing an insulating substrate and forming a via hole in the insulating substrate;
- forming a metal layer on an inner wall of the via hole;
- filling the via hole with a filler;
- forming a negative pattern for forming a circuit pattern on the insulating substrate, and selectively forming a negative pattern for forming a plating pattern in an end of the filler;
- and
- forming the circuit pattern and the plating pattern in the negative pattern for forming a circuit pattern and the negative pattern for forming a plating pattern, respectively.
A printed circuit board having a plating pattern buried in a via, comprising:
- an insulating substrate including an electrically insulating resin;
- a via hole passing through the insulating substrate;
- a via including a metal layer formed on an inner wall of the via hole and a filler charged in the via hole;
- a circuit layer including a circuit pattern buried in the insulating substrate and transmitting an electrical signal;
- and
- a plating pattern buried in an end of the filler.
Dependencies are inferred from the claim text.