Chip package structure and method of fabricating the same
AssigneeIndustrial Technology Research Institute
InventorsJui-Ching Hsieh, Pin Chang, Chung-De Chen, Li-Chi Pan, Yu-Jen Wang, Chin-Horng Wang
Life of this patent
Estimating the term…
Abstract
A chip package structure including a heat dissipation substrate, a chip and a heterojunction heat conduction buffer layer is provided. The chip is disposed on the heat dissipation substrate. The heterojunction heat conduction buffer layer is disposed between the heat dissipation substrate and the chip. The heterojunction heat conduction buffer layer includes a plurality of pillars perpendicular to the heat dissipation substrate. The aspect ratio of each pillar is between about 3:1 and 50:1.
Claims28
A chip package structure, comprising:
- a heat dissipation substrate;
- a chip, disposed on the heat dissipation substrate;
- and
- a heterojunction heat conduction buffer layer, disposed between the heat dissipation substrate and the chip, wherein the heterojunction heat conduction buffer layer includes a plurality of pillars perpendicular to the heat dissipation substrate and each of the pillars has an aspect ratio between about 3:1 and 50:1.
A method of fabricating a chip package structure, comprising:
- providing a heat dissipation substrate;
- forming a heterojunction heat conduction buffer layer on the heat dissipation substrate, wherein the heterojunction heat conduction buffer layer comprises a plurality of pillars perpendicular to the heat dissipation substrate;
- and
- bonding a chip onto the heterojunction heat conduction buffer layer.
Dependencies are inferred from the claim text.