Error detection device, error correction/error detection decoding device and method thereof

An error correction/error detection decoding method for decoding encoded data sequence wherein the encoded data sequence is regarding a data sequence having a specified bit length as a polynomial, dividing that polynomial by a generator polynomial for generating error detection code, adding the error detection code to that data sequence so that the remainder becomes 0, then encoding the data sequence to which the error detection code has been added by a specified encoding method, comprising steps of:

• calculating remainder values by dividing polynomials that correspond to each respective bit position by said generator polynomial beforehand, and saving those remainder values in a memory;
• decoding an encoded data sequence repeatedly;
• inputting together with a decoded data sequence indicating the decoded result, bit position information that indicates the proper bit position of each data of the decoded data sequence;
• in finding remainder values from said memory that correspond to the proper bit positions of data of the decoded data sequence that are not ‘0’, and performing bit-corresponding addition of each of found remainder values;
• determining that there is no error in the input data sequence when all of the bits of the addition result become ‘0’, otherwise determining that there is error;
• and
• stopping decoding of said encoded data at the instant that error is no longer detected.

An error detection device that detects whether or not input data sequence has error wherein the input data is created at an encoder by regarding a data sequence having a specified bit length as a polynomial, dividing that polynomial by a polynomial for generating error detection code and adding the error detection code to the data sequence so that the remainder becomes ‘0’, comprising:

• a remainder memory that saves remainder values that are obtained when polynomials corresponding to each respective bit position are divided by said generator polynomial;
• an addition unit to which, together with an input data sequence, bit position information that indicates the proper bit position of each data of the input data sequence is input, that finds remainder values from said remainder memory that correspond to the proper bit positions of data of the input data sequence that are not ‘0’, and performs bit-corresponding addition of each of the found remainder values;
• and
• an error judgment unit that determines that there is no error in the input data sequence when all of the bits of the addition result are ‘0’, otherwise determines that there is error.

An error correction/error detection decoding device that decodes encoded data sequence wherein the encoded data sequence is created at an encoder by regarding a data sequence having a specified bit length as a polynomial, divides that polynomial by a polynomial for generating error detection code, adding the error detection code to that data sequence so that the remainder becomes 0, then encoding the data sequence to which the error detection code has been added by a specified encoding method, comprising:

• a decoding unit that repeatedly decodes the encoded data sequence as an input data sequence;
• and
• an error detection unit that detects whether or not there is error in the decoded result, and notifies the decoding unit of the error detection result;
• wherein
• said decoding unit comprises:
• a decoder that repeatedly decodes the encoded data sequence and outputs the decoded result;
• a bit position management unit that outputs the proper bit position of each data of the decoded result;
• and
• a control unit that controls whether the decoding device continues or stops the decoding process;
• and
• said error detection unit comprises:
• a remainder memory that saves remainder values when polynomials that correspond to each respective bit position are divided by said generator polynomial;
• an addition unit to which, together with a decoded result bit position information that indicates the proper bit position of each data of the decoded result is input, that finds remainder values from said remainder memory that correspond to the proper bit positions of data of the decoded result that are not ‘0’, and performs bit-corresponding addition of each of the found remainder values;
• and
• an error judgment unit that determines that there is no error in the input data sequence when all of the bits of the addition result become ‘0’, otherwise determines that there is error;
• wherein
• said decoding unit stops decoding of said encoded data when error is no longer detected.