US 2010/0138709 A1Published application

Method and apparatus for delay fault coverage enhancement

OwnerLaung-Terng WANG, Michael S. Hsiao +4inventors

InventorsLaung-Terng WANG, Michael S. Hsiao, Hao-Jan Chao, Zhigang Jiang, Shianling Wu, Jianping Yan

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Abstract

A hybrid clocking scheme for simultaneously detecting a b-cycle path-delay fault in a b-cycle (false) path and a c-cycle path-delay fault in a c-cycle (false) path using at least n+1 at-speed clock pulses during a capture operation in a clock domain in a scan design or a scan-based BIST design, where 1<=b<=c<=n. The scan design or BIST design includes multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The design includes one or more clock domains each running at its intended operating frequency or at-speed. The hybrid clocking scheme comprises at least one at-speed shift clock pulse or one at-speed capture clock pulse immediately followed by at least two at-speed capture clock pulses during the capture operation to simultaneously detect the b-cycle path-delay fault and the c-cycle path-delay fault within the clock domain.

Claims20

Dependent claims

A method for providing an ordered sequence of n+1 clock pulses to a test clock for detecting a b-cycle path-delay fault in a b-cycle (false) path and a c-cycle path-delay fault in a c-cycle (false) path simultaneously, where 1<=b<=c<=n, in a clock domain in a scan design or a scan-based built-in self-test (BIST) design during test, the test clock driving the clock domain which contains one or more scan cells coupled in series, the test clock comprising at least a shift clock pulse and at least a capture clock pulse, each shift clock pulse running selectively at a selected reduced shift frequency (called slow-speed) or at the clock domain's intended operating frequency (called at-speed) in scan mode, each capture clock pulse running at-speed in normal mode;

said method comprising:
(a) Applying to the test clock one or more slow-speed or at-speed shift clock pulses to shift-in a test stimulus to all said scan cells in said clock domain, during a shift operation;
(b) Applying said ordered sequence of clock pulses to the test clock that comprises at least i at-speed shift clock pulses immediately followed by at least n+1−i at-speed capture clock pulses to capture the results into all said scan cells in response to said test stimulus, where 0<=i<n, during a capture operation;
wherein when detecting the b-cycle path-delay fault and the c-cycle path-delay fault simultaneously, the consecutive b−1 and c−1 at-speed shift or capture clock pulses prior to the last at-speed capture clock pulse that drive the b-cycle (false) path and the c-cycle (false) path are selectively suppressed or controlled to hold the state of the two paths' source flip-flops to ensure the correct capture of the output response, respectively;
and
(c) Applying to the clock domain one or more slow-speed or at-speed shift clock pulses to shift-out the output response of all said scan cells in said clock domain for analysis, during the shift operation.

3 more elements

An apparatus for providing an ordered sequence of n+1 clock pulses to a test clock for detecting a b-cycle path-delay fault in a b-cycle (false) path and a c-cycle path-delay fault in a c-cycle (false) path simultaneously, where 1<=b<=c<=n, in a clock domain in a scan design or a scan-based built-in self-test (BIST) design during test, the test clock driving the clock domain which contains one or more scan cells coupled in series, the test clock comprising at least a shift clock pulse and at least a capture clock pulse, each shift clock pulse running selectively at a selected reduced shift frequency (called slow-speed) or at the clock domain's intended operating frequency (called at-speed) in scan mode, each capture clock pulse running at-speed in normal mode;

said apparatus comprising:
(a) A first hardware for applying to the test clock one or more slow-speed or at-speed shift clock pulses to shift-in a test stimulus to all said scan cells in said clock domain, during a shift operation;
(b) A second hardware for said ordered sequence of clock pulses to the test clock that comprises at least i at-speed shift clock pulses immediately followed by at least n+1−i at-speed capture clock pulses to capture the results into all said scan cells in response to said test stimulus, where 0<=i<n, during a capture operation;
wherein when detecting the b-cycle path-delay fault and the c-cycle path-delay fault simultaneously, the consecutive b−1 and c−1 at-speed shift or capture clock pulses next to the last at-speed capture clock pulse that drive the b-cycle (false) path and the c-cycle (false) path are selectively suppressed or controlled to hold the state of the two path's source flip-flops to ensure the correct capture of the output response, respectively;
and
(c) A third hardware for applying to the clock domain one or more slow-speed or at-speed shift clock pulses to shift-out the output response of all said scan cells in said clock domain for analysis, during the shift operation.

3 more elements

Dependencies are inferred from the claim text.