Multi-Core Processing System for Vehicle Control Or An Internal Combustion Engine Controller
AssigneeHitachi Automotive Systems, Ltd.
InventorKeiichiro OHKAWA
Life of this patent
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Abstract
A vehicle control multi-core system for controlling a device mounted on a vehicle by using a plurality of cores, includes a computation process unit that is executed on the plurality of cores and required for the control of the device, and a core failure determination unit that compares a result of a computation process executed by the computation process unit at a specific timing on a specific core among the plurality of cores, with a result of a computation process executed by the computation process unit at a timing different from the specific timing on another core different from the specific core among the plurality of cores to determine that a failure occurs on the specific core.
Claims20
A vehicle control multi-core system for controlling a device mounted on a vehicle by using a plurality of cores, comprising:
- a computation process unit that is executed on the plurality of cores and required for the control of the device;
- and
- a core failure determination unit that compares a result of a computation process executed by the computation process unit at a specific timing on a specific core among the plurality of cores, with a result of a computation process executed by the computation process unit at a timing different from the specific timing on another core different from the specific core among the plurality of cores to determine that a failure occurs on the specific core.
An internal combustion engine controller including a plurality of cores to control an internal combustion engine, comprising:
- a computation process unit that is executed on the plurality of cores and required for a control of the internal combustion engine;
- and
- a core failure determination unit that compares a result of a computation process executed by the computation process unit at a specific timing on a specific core among the plurality of cores, with a result of a computation process executed by the computation process unit at a timing different from the specific timing on another core different from the specific core among the plurality of cores to determine that the failure occurs on the specific core.
Dependencies are inferred from the claim text.