Memory system with dynamic supply voltage scaling
AssigneeInternational Business Machines Corporation
InventorsKyu-hyoun Kim, Paul W. Coteus, Alan Gara, Vipin Patel, Kenneth L. Wright
Life of this patent
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Abstract
A memory controller, memory device, and method for dynamic supply voltage scaling in a memory system are provided. The method includes receiving a request for a supply voltage change at the memory controller in the memory system, the supply voltage powering the memory device. The method further includes waiting for any current access of the memory device to complete, and disabling a clock between the memory controller and the memory device. The method also includes changing the supply voltage responsive to the request, and enabling the clock.
Claims24
A memory device comprising:
- a memory core, the memory core responsive to a variable external supply voltage configurable by a memory controller between a lower power mode of operation and a higher power mode of operation.
A memory controller comprising:
- memory control logic to interface with a processor;
- a memory input/output interface to interface with a memory device;
- and
- supply voltage control logic to decrease supply voltage delivered from a power supply to the memory device in response to a request for a lower power mode of operation, and increasing the supply voltage delivered from the power supply to the memory device in response to a request for a higher power mode of operation.
A method comprising:
- receiving a request for a supply voltage change at a memory controller in a memory system, the supply voltage powering a memory device;
- waiting for any current access of the memory device to complete;
- disabling a clock between the memory controller and the memory device;
- changing the supply voltage responsive to the request;
- and
- enabling the clock.
A design structure tangibly embodied in a machine-readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:
- memory control logic to interface with a processor;
- a memory input/output interface to interface with a memory device;
- and
- supply voltage control logic to decrease supply voltage delivered from a power supply to the memory device in response to a request for a lower power mode of operation, and increasing the supply voltage delivered from the power supply to the memory device in response to a request for a higher power mode of operation.
Dependencies are inferred from the claim text.