Semiconductor device
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorKiyoshi Kato
Life of this patent
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Abstract
A semiconductor device capable of stabilizing power supply by suppressing power consumption as much as possible. The semiconductor device of the invention includes a central processing unit having a plurality of units and a control circuit, and an antenna. The control circuit includes a means for outputting, based on a power supply signal including data on power supply from an antenna (through an antenna) or a load signal obtained by an event signal supplied from each of the units, one or more of a first control signal for stopping power supply to one or more of the units, a second control signal for varying a power supply potential supplied to one or more of the units, and a third control signal for stopping supplying a clock signal to one or more of the units.
Claims22
A semiconductor device comprising:
- a plurality of memory blocks;
- a control circuit;
- and
- a power supply circuit,
- wherein each of the memory blocks comprises:
- a memory cell array including a plurality of memory cells each having a memory element in a region where a bit line and a word line cross each other with an insulator interposed therebetween;
- and a row decoder connected to the word line;
- and
- the control circuit outputs to the power supply circuit, based on an operation signal including operating data of the memory blocks, at least one of a first control signal for varying a power supply potential supplied to the memory cell array, and a second control signal for stopping a power supply potential supplied to the row decoder.
A semiconductor device comprising:
- a plurality of memory blocks;
- a control circuit;
- a power supply circuit;
- and
- a plurality of switches provided between the memory blocks and the power supply circuit, wherein each of the plurality of switches corresponds to one of the plurality of memory blocks,
- wherein each of the memory blocks comprises:
- a memory cell array including a plurality of memory cells each having a memory element in a region where a bit line and a word line cross each other with an insulator interposed therebetween;
- and a row decoder connected to the word line;
- and
- the control circuit outputs to the switches, based on an operation signal including operating data of the memory blocks, at least one of a first control signal for varying a power supply potential supplied to the memory cell array, and a second control signal for stopping a power supply potential supplied to the row decoder.
Dependencies are inferred from the claim text.