Devices, systems, and methods to synchronize parallel processing of a single data stream
AssigneeMicron Technology, Inc.
InventorHarold B Noyes
Life of this patent
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Abstract
Disclosed are methods and devices, among which is a system that includes one or more pattern-recognition processors, such as in a pattern-recognition cluster. The pattern-recognition processors may be activated to perform a search of a data stream individually using a chip select or in parallel using a universal select signal. In this manner, the plurality of pattern-recognition processors may be enabled concurrently for synchronized processing of the data stream.
Claims27
A device, comprising:
- a plurality of processors, wherein each of the plurality of processors comprises a chip select input adapted to receive a chip select signal and a universal select input adapted to receive a universal select signal, wherein the chip select signal is one of a plurality of chip select signals, each of which being adapted to activate a respective one of the plurality of processors, and the universal select signal is adapted to activate the plurality of processors concurrently.
A system for processing data in parallel comprising:
- a plurality of processing circuits adapted to process data;
- address decode circuitry adapted to individually activate each of the plurality of processing circuits;
- a data bus adapted to transmit data to each of the plurality of processing circuits;
- and
- a universal select line adapted to transmit a universal select signal to the plurality of processing circuits for concurrent activation of the plurality of processing circuits, wherein the plurality of processing circuits is adapted to process the data synchronously upon activation by the universal select signal.
A method for processing data comprising:
- activating a plurality of processing circuits by a universal chip select signal when a stream of data is to be synchronously processed in parallel by the plurality of processing circuits;
- receiving the stream of data at the plurality of processing circuits;
- and
- synchronously processing the stream of data concurrently in the processing circuits.
A method of processing data, comprising:
- activating address decode circuitry to transmit a chip select signal for activating one of a plurality of processing circuits when a stream of data is to be processed by the one of the plurality of processing circuits;
- activating the plurality of processing circuits by a universal select signal when the stream of data is to be processed in parallel by the plurality of processing circuits;
- receiving the stream of data at all activated processing circuits;
- and
- processing the stream of data at all the activated processing circuits.
A device, comprising:
- a plurality of data processing circuits;
- address decode circuitry adapted to selectively activate at least one of the plurality of data processing circuits;
- and
- a universal select line adapted to transmit a universal select signal to the plurality of data processing circuits for concurrent activation of the plurality of data processing circuits.
Dependencies are inferred from the claim text.