Memory Area Protection System and Methods
AssigneeMicron Technology, Inc.
InventorsLuca De Santis, Maria Luisa Gallese, Giuliano Gennaro Imondi
Life of this patent
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Abstract
In one embodiment, a non-volatile memory device includes a plurality of protection bits denoting that an area of memory in the device must be protected from being erased or programmed. The memory device further includes a majority logic circuit for determining the logic state of the majority of the plurality of protection bits. Another embodiment includes a pattern generator for generating the logic levels to be stored in the plurality of protection bits.
Claims38
A method of protecting a memory area comprising:
- computing a logical value based on the data stored in a plurality of the memory cells;
- and
- preventing the memory cells in the memory area from being programmed responsive to the logical value being a first value.
A memory area protection system comprising:
- a plurality of memory cells;
- a logic circuit coupled to the plurality of memory cells and operable to generate protection bits according to the data stored in a predetermined number of the plurality of memory cells;
- a register coupled to the logic circuit and operable to prevent the memory cells in the memory area from being programmed responsive to the protection bits having a first value.
A memory device comprising:
- an array of memory cells comprising a first and a second set of memory cells;
- a first logic circuit coupled to the first set of the memory cells and operable to determine a logical state according to the data stored in the memory cells in the first set of memory cells;
- a second logic circuit coupled to the memory cells in the second set of memory cells and to the first logic circuit and operable to prevent the memory cells in the second set of memory cells from being programmed responsive to the logical state having a first value.
A system comprising:
- a processor operable to process data and to provide memory commands and addresses;
- and
- a memory device comprising:
- an array of memory cells comprising a first and a second set of memory cells;
- a first logic circuit coupled to the first set of the memory cells and operable to determine a logical state according to the data stored in the memory cells in the first set of memory cells;
- and
- a second logic circuit coupled to the memory cells in the second set of memory cells and to the first logic circuit and operable to prevent the memory cells in the second set of memory cells from being programmed responsive to the logical state having the first value.
A method of protecting a memory area comprising:
- reading the data from a plurality of memory cells;
- preventing the memory area from being programmed if more than a predetermined number of bits of the data read have a predetermined value.
A wireless telephone comprising:
- telephone circuitry including a memory device, comprising:
- an array of memory cells comprising a first and a second set of memory cells;
- a first circuit coupled to the first set of the memory cells and operable to determine a logical state according to the data stored in the memory cells in the first set of memory cells;
- and
- a second circuit coupled to the memory cells in the second set of memory cells and to the first circuit and operable to prevent memory cells in the second set of memory cells from being programmed responsive to the logical state having a first value.
Dependencies are inferred from the claim text.