Method and apparatus for inclusion of tlb entries in a micro-op cache of a processor

An apparatus for maintaining inclusion of a TLB (translation look-aside buffer) in a processor, the apparatus comprising:

• a micro-op cache to store micro-ops for execution by the processor;
• a TLB entry including a micro-op cache portion inclusion field associated with the TLB entry, operatively being set responsive to accessing the TLB entry;
• and
• inclusion logic coupled with the micro-op cache and the TLB, and being responsive to a replacement or an invalidation of the TLB entry, to flush the micro-op cache portion and clear a plurality of inclusion fields for the micro-op cache portion whenever the micro-op cache portion inclusion field associated with the replaced or invalidated TLB entry was set.

An article of manufacture including a machine readable medium, said machine readable medium storing state and/or executable data, which when accessed by one or more machines causes said one or more machines to:

• record, for a first micro-op cache line, a first instruction-cache way storing a first instruction corresponding to one or more micro-ops, generated by decoding the first instruction, and to be stored in the first micro-op cache line;
• update, responsive to a micro-op cache hit at the first micro-op cache line, an instruction-cache in-use indication associated with the first instruction, said instruction-cache in-use indication associated with the first instruction being located at least in part through use of the first instruction-cache way recorded for the first micro-op cache line;
• evict the first micro-op cache line corresponding to the recorded first instruction-cache way, and initiate a micro-op cache miss synchronization responsive to an eviction of the first instruction from the instruction-cache;
• and
• enqueue a victim-cache deallocation micro-op following the micro-op cache miss synchronization.