US 2010/0138608 A1 · Method and apparatus for pipeline inclusion and instruction restarts in a micro-op cache of a processor

Abstract

Methods and apparatus for instruction restarts and inclusion in processor micro-op caches are disclosed. Embodiments of micro-op caches have way storage fields to record the instruction-cache ways storing corresponding macroinstructions. Instruction-cache in-use indications associated with the instruction-cache lines storing the instructions are updated upon micro-op cache hits. In-use indications can be located using the recorded instruction-cache ways in micro-op cache lines. Victim-cache deallocation micro-ops are enqueued in a micro-op queue after micro-op cache miss synchronizations, responsive to evictions from the instruction-cache into a victim-cache. Inclusion logic also locates and evicts micro-op cache lines corresponding to the recorded instruction-cache ways, responsive to evictions from the instruction-cache.

Claims18

Dependent claims

An apparatus comprising:

a processor including a front end unit to obtain and decode instructions, the front end unit including:
a first cache including a plurality of entries each to store at least part of one or more instructions, each entry including a snoop field to store a snoop indicator to indicate that an instruction stored in the entry was hit by a snoop request and a use field to store a use indicator to indicate that an instruction stored in the entry was output to the front end unit;
and
a second cache including a plurality of entries each to store at least part of one or more micro-operations, wherein the second cache is to be maintained inclusively in the first cache, and wherein micro-operations of an instruction stored in a first entry of the first cache having a set snoop indicator are to be prevented from insertion into the second cache.

1 more element

An article comprising a machine-accessible storage medium including instructions that when executed cause a system to:

receive a snoop request in a first cache including a plurality of entries each to store at least part of one or more instructions, each entry including a snoop field to store a snoop indicator to indicate that an instruction stored in the entry was hit by a snoop request and a use field to store a use indicator to indicate that an instruction stored in the entry was output to a front end unit, and to set a corresponding the snoop indicator of a first entry of the first cache on the receipt;
maintain a second cache including a plurality of entries each to store at least part of one or more micro-operations inclusively with the first cache;
and
prevent micro-operations stored in the first entry of the first cache having a set snoop indicator from insertion into the second cache.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

12/317,959Filed 31 Dec 2008

Priority

2 Dec 2008

Published

3 Jun 2010

Term ends

Not estimatedThe source records don’t support an estimate.

Classification8 codes

G06F 12/0806
Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches: multiuser,…
G06F 12/0864
Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches: using…
G06F 12/0875
Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches: with…
G06F 12/1045
Using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]: associated with a data cache

Method and apparatus for pipeline inclusion and instruction restarts in a micro-op cache of a processor

Life of this patent

Method and apparatus for pipeline inclusion and instruction restarts in a micro-op cache of a processor

Life of this patent

Abstract

Claims18