Memory devices with buffered command address bus
AssigneeRound Rock Research, LLC
InventorPaul A. LaBerge
Life of this patent
Estimating the term…
Abstract
Circuits and methods are provided that alleviate overloading of the command address bus and limit decreases in command address bus bandwidth to allow increased numbers of memory modules to be included in a computer system. A plurality of switches is coupled between the command address bus (which is coupled to the memory controller) and a respective plurality of memory modules. Each switch provides command address bus data only to its respective memory module. Preferably, only one switch does so at a time, limiting the loading seen by the memory controller.
Claims21
1-36. (canceled)
A memory system comprising:
- a memory controller coupled to a bus switch, wherein:
- said memory controller provides a chip select signal to said bus switch, wherein the chip select signal controls an operation of said bus switch, and
- said memory controller provides command address bus signals to said bus switch, wherein said memory controller is synchronized by sending said command address bus signals early relative to the chip select signal to compensate for propagation delay added to said command address bus signals by said bus switch;
- and
- a memory module coupled to said command address bus signals via said bus switch.
A method for providing a memory system, comprising:
- transmitting a chip select signal to a bus switch from a memory controller, wherein the chip select signal controls an operation of said bus switch;
- transmitting command address bus signals to said bus switch from said memory controller, wherein said command address bus signals are transmitted early relative to the chip select signal to compensate for propagation delay added to said command address bus signals by said bus switch;
- and
- coupling said command address bus signals via said bus switch to a memory module.
A method for providing a memory system, comprising:
- transmitting a first chip select signal to a first bus switch and a second chip select signal to a second bus switch from a memory controller,
- transmitting command address bus signals to said first and second bus switches from said memory controller, wherein:
- said command address bus signals are transmitted early relative to the first and second chip select signals to compensate for propagation delay added to said command address bus signals by said first and second bus switches, and
- each of said first and second bus switches has an ON state and an OFF state, only one of said first and second switches being in the ON state at a time, wherein said first and second bus switches are selected to be in the ON state respectively by said first and second chip select signals;
- coupling said command address bus signals via said first switch to a first dual in-line memory module;
- coupling said command address bus signals via said second switch to a second dual in-line memory module;
- transmitting the command address bus signals to a respective one of said first and second dual in-line memory modules using said respective one of said first and second switches, when a respective one of said first and second switches is in the ON state;
- and
- isolating the command address bus signals from a respective one of said first and second dual in-line memory modules using said respective one of said first and second switches, when a respective one of said first and second switches is in the OFF state.
Dependencies are inferred from the claim text.