Memory controller and a method of operating an electrically alterable non-volatile memory device

A method of determining the integrity of data signals stored in an array of non-volatile memory cells, wherein the array of non-volatile memory cells is characterized by a plurality of blocks with each block having a plurality of non-volatile memory cells that are erased together, said method comprising:

• a) reading data from each of the memory cells from one of said blocks;
• b) correcting said data read, if need be, to form corrected data;
• c) writing corrected data, if exists, to a different block of said array, and not writing the data read if the data read is uncorrected;
• and
• d) repeating the steps (a)-(c) for different blocks of the array until all of the blocks have been read.

A method of determining the integrity of data signals stored in an array of non-volatile memory cells, wherein the array of non-volatile memory cells is characterized by a plurality of blocks with each block having a plurality of non-volatile memory cells that are erased together, said method comprising:

• a) reading the data signal from each of the memory cells from one of said blocks;
• b) comparing the data signal read to a margin signal;
• c) writing the data corresponding to the data signal into a different memory cell of a different block of said array, in the event the result of the comparing step (b) indicates the necessity of writing the data corresponding to the data signal to a different memory cell, and not writing the data if otherwise;
• and
• d) repeating the steps (a)-(c) for different blocks of the array until all of the blocks have been read.

A controller for operating a non-volatile memory device having an array of non-volatile memory cells, susceptible to suffering loss of data stored in one or more memory cells of said array, said controller for interfacing with a host device and for receiving, from the host device a time-stamp signal, said controller comprising:

• a processor;
• a memory having program code stored therein for execution by the processor, said program code configured to:
• receiving by the controller the time stamp signal from the host device;
• comparing the received time stamp signal with a stored signal wherein the stored signal is a time stamp signal received earlier in time by the controller from the host device;
• and
• determining when to perform a data retention and refresh operation for data stored in the memory array based upon the comparing step.

A controller for operating a non-volatile memory device having an array of non-volatile memory cells, with said array of non-volatile memory cells having a plurality of blocks with each block having a plurality of memory cells that are erased together, said controller comprising:

• a processor;
• a memory having program code stored therein for execution by the processor, said program code configured to:
• a) reading data from each of the memory cells from one of said blocks;
• b) correcting said data read, if need be, to form corrected data;
• c) writing corrected data, if exists, to a different block of said array, and not writing the data read if the data read is uncorrected;
• and
• d) repeating the steps (a)-(c) for different blocks of the array until all of the blocks have been read.

A controller for operating a non-volatile memory device having an array of non-volatile memory cells, with said array of non-volatile memory cells having a plurality of blocks with each block having a plurality of memory cells that are erased together, said controller comprising:

• a processor;
• a memory having program code stored therein for execution by the processor, said program code configured to:
• a) reading the data signal from each of the memory cells from one of said blocks;
• b) comparing the data signal read to a margin signal;
• c) writing the data corresponding to the data signal into a different memory cell of a different block of said array, in the event the result of the comparing step (b) indicates the necessity of writing the data corresponding to the data signal to a different memory cell, and not writing the data if otherwise;
• and
• d) repeating the steps (a)-(c) for different blocks of the array until all of the blocks have been read.