Devices, systems, and methods to synchronize simultaneous dma parallel processing of a single data stream by multiple devices
AssigneeMicron Technology, Inc.
InventorHarold B Noyes
Life of this patent
Estimating the term…
Abstract
Disclosed are methods and devices, among which is a system that includes a device that includes one or more pattern-recognition processors in a pattern-recognition cluster, for example. One of the one or more pattern-recognition processors may be initialized to perform as a direct memory access master device able to control the remaining pattern-recognition processors for synchronized processing of a data stream.
Claims26
An electronic device, comprising:
- a plurality of pattern-recognition processors, wherein each of the plurality of pattern-recognition processors comprises a parallel direct memory access (PDMA) master/slave input adapted to place that processor into a master or a slave mode, and a PDMA cycle connection adapted to transmit a direct memory access cycle from that processor, when placed into a master mode, to each of the plurality of pattern-recognition processors placed into a slave mode concurrently.
An electronic system for processing data in parallel comprising:
- a processing unit adapted to activate a direct memory access (DMA) master device;
- and
- a plurality of processing circuits adapted to process a data stream concurrently and independently of the processor, wherein the plurality of processing circuits includes the DMA master device and one or more DMA slave devices adapted to concurrently respond to DMA bus cycles.
A method for processing data comprising:
- activating a direct memory access (DMA) master device adapted to control the synchronous processing of a stream of data amongst the DMA master device and one or more DMA slave devices;
- receiving the stream of data at the DMA master device and the one or more DMA slave devices;
- and
- synchronously processing the stream of data in the DMA master device and the one or more DMA slave devices.
A method of processing data, comprising:
- activating one of a plurality of processing circuits when a stream of data is to be processed singularly by the one of the plurality of processing circuits;
- activating a plurality of processing circuits when the stream of data is to be processed in parallel by the plurality of processing circuits;
- activating one of the plurality of processing circuits as a direct memory access (DMA) master device adapted to control the synchronous processing of the stream of data amongst the plurality of processing circuits if the plurality of processing circuits are activated;
- receiving the stream of data at all activated processing circuits concurrently;
- and
- concurrently processing the stream of data at all the activated processing circuits.
An electronic device, comprising:
- a processing unit adapted to transfer processing of a data stream to a plurality of processing circuits;
- and
- a plurality of processing circuits adapted to process the data stream concurrently and transmit the results to the processing unit, wherein the plurality of processing circuits includes a DMA master device and one or more DMA slave devices.
An electronic device, comprising:
- a plurality of pattern-recognition processors, wherein each of the plurality of pattern-recognition processors comprises a parallel direct memory access (PDMA) master/slave input adapted to place that processor into a master or a slave mode, and a PDMA connection adapted to receive DMA bus cycles concurrently.
Dependencies are inferred from the claim text.