Receiver with Clock Recovery Circuit and Adaptive Sample and Equalizer Timing
AssigneeRambus Inc.
InventorsQi Lin, Brian Leibowitz, Hae-Chang Lee, Jihong Ren, Kyung Suk Oh, Jared Zerbe
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Abstract
A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.
Claims24
1-33. (canceled)
A receiver, comprising:
- a data input;
- a clock recovery circuit to produce to produce a timing reference signal from the data input;
- an equalizer to equalize the data input to provide an equalized signal;
- a sampler that generates samples of the equalized signal according to a sampling clock;
- a circuit to set the sampling clock relative to the timing reference signal using feedback, the circuit adjusting the sampling clock toward a value that maximizes a quality measure in the equalized signal, the quality measure based on at least one of (i) post-equalized voltage margin, (ii) on post-equalized timing margin, or (iii) minimized bit error rate.
In a receiver having a clock recovery circuit that generates a clock signal based on transitions in an input signal, an equalizer that equalizes the input signal to produce an equalized signal, and a sampler that samples the equalized input signal, an improvement comprising:
- sampling the equalized input signal with the sampler at timing determined by a sampling clock;
- with respect to multiple samples, adjusting the sampling clock while determining a measure of quality derived from the equalized input signal;
- determining a point of inflexion of the measure of quality;
- and
- setting the sampling clock in dependence on the point of inflexion;
- wherein the measure of quality is dependent on at least one of voltage margin, timing margin or bit error rate;
- and
- wherein the receiver sets the sampling clock to correspond to a phase of the clock signal based upon quality feedback measured post-subtraction of equalization provided by the equalizer.
In a receiver having a clock recovery circuit that generates a clock signal based on transitions in an input signal, the receiver producing a sampling clock to time sampling of the input signal relative to the sampling clock, the receiver having a sampler to produce digital samples representing the input signal according to the sampling clock, an improvement comprising:
- setting the sampling clock to be offset from the clock signal to approximately correspond to approximately expected maximum data eye voltage margin;
- and
- adjusting the sampling clock away from the approximately maximum data eye voltage margin in dependence upon a quality measure, the quality measure selected to be a value based upon current symbol voltage margin and precursor symbol voltage margin.
A receiver, comprising:
- a data input;
- means for producing a reference clock signal;
- an equalizer to equalize the data input to produce an equalized signal;
- a sampler that generates samples of the equalized signal according to a sampling clock;
- means for adjusting the sampling clock relative to the timing reference signal toward a value that maximizes a quality measure in the equalized signal, the quality measure based on at least one of (i) post-equalized voltage margin, (ii) post-equalized timing margin, or (iii) minimized bit error rate.
Dependencies are inferred from the claim text.