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US 2010/0135373 A1Published application
Clock generating device and jitter reducing method in the clock generating device
AssigneeSeiko Epson Corporation
InventorHideaki YAMADA
Life of this patent
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Abstract
A clock generating device includes: a DDS circuit that generates a periodic signal; and a comparator that compares an input signal and a reference signal and outputs a binary signal. The clock generating device includes a rate-of-change correcting unit that applies correction for increasing a rate of change at a crossing point with the reference signal to the periodic signal generated by the DDS circuit.
Claims4
A clock generating device comprising:
- a DDS circuit that generates a periodic signal;
- and
- a comparator that compares an input signal and a reference signal and outputs a binary signal, wherein
- the clock generating device includes a rate-of-change correcting unit that applies correction for increasing a rate of change at a crossing point with the reference signal to the periodic signal generated by the DDS circuit.
1 more element
A jitter reducing method for a clock generating device including:
- a DDS circuit that generates a periodic signal;
- and
- a comparator that compares an input signal and a reference signal and outputs a binary signal,
- the jitter reducing method comprising applying correction for increasing a rate of change at a crossing point with the reference signal to the periodic signal generated by the DDS circuit.
1 more element
Dependencies are inferred from the claim text.