Precesion/speed compromise of a synchronization signal reception device

Reception device able to receive packets in a packet communication network comprising at least two stations, the said device comprising:

• means for receiving packets containing samples of the said network, the said samples originating from data sampled every period Tsmp, where Tsmp emanates from a time base synchronized on all the stations of the said network;
• means for regenerating a counting ramp with the aid of a phase-locked loop receiving the samples and furthermore delivering local samples every period Tsmp and a reconstituted clock;
• means for initializing, on every zero-crossing of the counting ramp, an image counter which is regulated by the reconstituted clock;
• means for generating image pips every zero-crossing of the said image counter;
• and
• means for reconstituting a synchronization signal on the basis of the said image pips;
• the phase-locked loop comprising:
• a samples comparator comparing the samples and the local samples and delivering an error signal;
• a corrector receiving the signal and delivering a corrected error signal, the corrector having a static gain equal to 1;
• a digital oscillator receiving the corrected error signal and delivering the reconstituted clock, the clock having a frequency dependent on the signal and being proportional to a gain;
• wherein the phase-locked loop comprises, furthermore, a gain adjustment device which determines a gain value as a function of the error signal.