System of sampling interface for an optical pick-up head
AssigneeTian Holdings, LLC
InventorChih-Min Liu
Life of this patent
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Abstract
A system of sampling interface for an optical pick-up head comprises an optical pick-up head, a PMOS, a boost circuit, and a sample and hold circuit. The optical pick-up head outputs one of a reading voltage and a writing voltage. The PMOS gate receives the gate voltage and then the PMOS is turned on to pass the reading voltage to the sample and hold circuit. Moreover, the substrate of the PMOS receives a control voltage. The boost circuit is used to boost the gate voltage higher than the control voltage for turning off the PMOS and isolating the writing voltage.
Claims22
A system of sampling interface for an optical pick-up head, said system comprising:
- said optical pick-up head for outputting one of a reading voltage and a writing voltage;
- a first P-TYPE Metal Oxide Semiconductor device (PMOS) comprising a first source/drain, a first PMOS gate and a substrate, and wherein said first source/drain is for receiving one of said reading voltage and said writing voltage, and said first PMOS gate receives a gate voltage for turning on a path between said first source/drain of said first PMOS and a second source/drain of said first PMOS, and said substrate receives a control voltage;
- a boost circuit connecting with said first PMOS gate for boosting said gate voltage up to higher than said control voltage and turning off a path between said first source/drain and said second source/drain so as to block said writing voltage;
- and
- a sample and hold circuit connecting with said second source/drain for sampling and holding said reading voltage.
A system of sampling interface for an optical pick-up head, said system comprising:
- said optical pick-up head for outputting one of a reading voltage and a writing voltage;
- a first PMOS comprising a first source/drain, a first PMOS gate and a substrate, and wherein said first source/drain is for receiving one of said reading voltage and said writing voltage, and said first PMOS gate receives a gate voltage for turning on a path between said first source/drain and a second source/drain of said first PMOS, and said substrate connects with said first source/drain;
- a voltage regulation circuit connecting with said first PMOS gate, wherein said voltage regulation circuit controls said first PMOS by a sample signal to output said reading voltage and block said writing voltage;
- and
- a sample and hold circuit sampling said reading voltage of said second source/drain according to said sample signal.
Dependencies are inferred from the claim text.