Semiconductor memory devices having redundancy arrays
AssigneeSamsung Electronics Co., Ltd.
InventorKyo-hyun Kyung
Life of this patent
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Abstract
A semiconductor memory device includes a plurality of memory areas. Each of the memory areas includes a normal cell array and a redundancy cell array for repairing defective cells generated in the normal cell array such that the semiconductor memory device is usable even when memory arrays include defective cells. A size of a redundancy cell array of a first memory area is greater than a size of the redundancy cell arrays of the other memory areas.
Claims15
A semiconductor memory device including a plurality of memory areas, each of the memory areas comprising:
- a normal cell array;
- and
- a redundancy cell array for repairing defective cells generated in the normal cell array,
- wherein a size of the redundancy cell array of a first memory area of the plurality of memory areas is greater than sizes of the redundancy cell arrays of other memory areas of the plurality of memory areas.
A semiconductor memory device including a plurality of memory areas, the plurality of memory areas comprising:
- a first memory area including a first normal cell array and a first redundancy cell array, and storing information regarding system software;
- and
- a second memory area including a second normal cell array and a second redundancy cell array, and storing data,
- wherein a size of the first redundancy cell array of the first memory area is different from a size of the second redundancy cell array of the second memory area.
Dependencies are inferred from the claim text.