Apparatus and method for trimming static delay of a synchronizing circuit

A memory device, comprising:

• a memory cell array configured to store data written to the array at and
• a clock signal generator circuit operable to generate a clock signal, the clock signal generator comprising:
• a delay-locked loop (DLL) having a DLL adjustable delay and a phase detector, the DLL adjustable delay operable configured to provide a first delayed clock signal in response to a first input clock signal and further operable to provide a second delayed clock signal in response to second input clock signal, the first and second input clock signals being complementary, the phase detector operable configured to compare first and second signals and further operable to adjust the delay of the DLL adjustable delay based on the phase of the first and second signals;
• and
• a trimming circuit having first and second adjustable delays circuits and operable configured to trim an uncorrected duty cycle by delaying delay the first and second delayed clock signals, respectively, provided by the DLL adjustable delay by respective first and second adjustable delays that are within a range extending from a respective intrinsic delay to a respective maximum delay to provide respective first and second output clock signals, one of the first and second adjustable delay circuits being set at the intrinsic delay of the respective delay circuit and the other of the first and second adjustable delay circuits being set at a delay that is less than the maximum delay of the respective delay circuit, the first input clock signal and the first output clock signal provided to the phase detector as the first and second signals.

A memory device, comprising:

• a memory cell array configured to store data written to the array;
• and
• a clock signal generator circuit, comprising:
• a delay circuit configured to provide a delayed clock signal in response to an input clock signal, the delayed clock signal having a timing relative to a timing of the input clock signal that is determined by a comparison of respective timings of first and second signals, the delayed clock signal being used to provide a feedback clock signal;
• and
• a trimming circuit having first and second adjustable delays circuits and configured to delay the input clock signal and the feedback clock signal, respectively, by respective adjustable first and second adjustable delays to provide the first and second signals, respectively, to the phase detector, one of the first and second adjustable delay circuits being set at the intrinsic delay of the respective delay circuit and the other of the first and second adjustable delay circuits being set at a delay that is less than the maximum delay of the respective delay circuit.

A memory device, comprising:

• a memory cell array configured to store data written to the array;
• and
• a clock signal generator circuit, comprising:
• a delay circuit configured to provide a first delayed clock signal by delaying a first input clock signal and to provide a second delayed clock signal by delaying a second input clock signal, the first and second input clock signals being complementary, the delayed clock signals having respective timings relative to timings of the respective input clock signals that are determined by a comparison of respective timings of first and second signals;
• and
• a trimming circuit having first and second adjustable delay circuits configured to delay the first and second delayed clock signals by respective adjustable first and second adjustable delays that are each within a range extending from a respective intrinsic delay to a respective maximum delay to provide the first and second signals, one of the first and second adjustable delay circuits being set at the intrinsic delay of the respective delay circuit and the other of the first and second adjustable delay circuits being set at a delay that is less than the maximum delay of the respective delay circuit.