Method and apparatus for synchronization of row and column access operations

A semiconductor memory device, comprising:

• an array of memory cells;
• and
• a memory array interface circuit coupled to the array of memory cells, the memory array interface comprising:
• a first delay means for delaying a wordline timing pulse by a first predetermined delay amount to provide a first delayed wordline timing pulse;
• a first logic circuit, coupled to the first delay means, for logically combining the wordline timing pulse and the first delayed wordline timing pulse to provide a sense amplifier enable signal;
• a second delay means for delaying the wordline timing pulse by a second predetermined delay amount, that is greater than the first predetermined delay amount, to provide a second delayed wordline timing pulse;
• a second logic circuit, coupled to the second delay means, for logically combining the wordline timing pulse and the second delayed wordline timing pulse to provide a column select enable signal;
• and
• enabling circuitry, coupled to the first and second logic circuits and to a sense amplifier power supply circuit of the memory array and a plurality of column access devices of the memory array, the enabling circuitry being configured to enable:
• the sense amplifier power supply circuit in response to the sense amplifier enable signal, and
• selected ones of the plurality of column access devices in response to the column select enable signal, after the sense amplifier power supply circuit is enabled.