Fabrication method and structure of semiconductor non-volatile memory device

A non-volatile semiconductor memory device, comprising:

• a semiconductor substrate;
• first and second semiconductor regions of a first conductivity type formed in said semiconductor substrate;
• a first channel region and a second channel region of a second conductivity type formed between said first semiconductor region and said second semiconductor region in said semiconductor substrate, said first channel region being located on the side close to said first semiconductor region and said second channel region being located on the side close to said second semiconductor region;
• a first gate formed above said first channel region via a first insulator;
• and
• a second gate formed above said second channel region via a second insulator,
• wherein writing and erasing operations are performed by injecting electrons and holes into said second insulator, respectively, and such that for implementing each erasing operation a voltage pulse having a first polarity and a different voltage pulse having a second, opposing polarity are applied to said second gate and said second semiconductor region, respectively, a plural number of times.

A non-volatile semiconductor memory device including a plurality of memory cells formed at a principal surface of a semiconductor substrate, wherein each of the non-volatile memory cells comprises:

• first and second semiconductor regions of a first conductivity type formed in said semiconductor substrate;
• a first channel region and a second channel region between said first semiconductor region and said second semiconductor region in said semiconductor substrate, said first channel region being located on the side close to said first semiconductor region and said second channel region being located on the side close to said second semiconductor region,
• wherein the charge density of an impurity in said first channel region is different from the charge density of an impurity in said second channel region;
• a first gate formed above said first channel region via a first insulator;
• and
• a second gate formed above said second channel region via a second insulator,
• wherein said non-volatile memory is enabled to at least perform a writing operation in which electrons are injected into said second insulator, an erasing operation in which holes are injected into said second insulator and a holding operation in which charges are held in said second insulator, and such that for the erasing operation an erasing pulse is applied to said second gate and to said second semiconductor region two or more times.