Method of driving a gate line, gate drive circuit and display apparatus having the gate drive circuit

A gate drive circuit including cascaded stages, the cascaded stages including a first stage to which a scan start signal is provided to an input terminal thereof, each stage of the cascaded stages comprising:

• a charging section which charges one of the scan start signal and a carry signal provided from a previous stage to a first node;
• a driving section connected to the charging section at the first node, the driving section configured to pull up a high level of a first clock signal to output a gate signal through a gate node as the first node is charged to a high level;
• a first discharging section which discharges a voltage potential of the first node and a voltage potential of the gate node to hold the voltage potential of the first node and the voltage potential of the gate node at a first power voltage as the first clock signal is shifted to a low level;
• and
• a second discharging section which receives a voltage potential signal of a second node of a previous stage, which holds a gate signal outputted from the previous stage, to reduce ripples generated at the first node.

A display apparatus comprising:

• a display panel comprising pixel parts connected to gate lines and data lines crossing the gate lines;
• a data drive circuit which provides the data lines with a data voltage;
• and
• a gate drive circuit having cascaded stages,
• wherein each of the plural stages comprises:
• a charging section which charges one of a scan start signal and a carry signal provided from a previous stage to a first node;
• a driving section connected to the charging section at the first node, the driving section configured to pull up a high level of a first clock signal to output a gate signal through a gate node as the first node is charged to a high level;
• a first discharging section which discharges a voltage potential of the first node and a voltage potential of the gate node to hold the voltage potential of the first node and the voltage potential of the gate node to a first power voltage as the first clock signal is shifted to a low level;
• and
• a second discharging section which receives a voltage potential signal of a second node of a previous stage, which holds a gate signal outputted from the previous stage, to reduce ripple components generated at the first node.