Apparatus for compensating for error of time-to-digital converter

An apparatus for compensating for an error of a TDC, which receives a delay phase and a TDC error-contained phase error from a phase detector including the TDC, the apparatus comprising:

• first to Mth multipliers fragmenting the delay phase by ½ to ½M times;
• first to (2M−1)th adder adding the phase error to an output from the first multiplier, and adding and subtracting an output of an upper comparator to and from each of outputs from the second to Mth multipliers;
• and
• first to Mth comparators comparing the phase error and an output from the first adder and comparing the output from the upper comparator and outputs from mutually adjacent adders among the second to the (2M−1)th adders to acquire a phase error compensation value nearest to an actual phase error.

An apparatus for compensating for an error of a TDC, which receives a delay phase and a TDC error-contained phase error from a phase detector including the TDC, the apparatus comprising:

• a primary comparison unit adding a delay phase, which has been fragmented by ½ times, to the phase error, and comparing the resultant value with the phase error;
• a multiplexer receiving an output from the primary comparison unit and a phase error correction value, selectively outputting an output from the primary comparison unit when a control signal has a first value, and selectively outputting the phase error correction value when the control signal has a second value;
• and
• a secondary comparison unit adding or subtracting a delay phase, which has been fragmented by ½M (M is a natural number of 2 or larger), to and from an output from the multiplexer, and comparing the resultant value with the output from the multiplexer to acquire a phase error compensation value nearest to an actual phase error.