Arithmetic decoding apparatus

An arithmetic decoding apparatus comprising:

• an instruction decoder configured to decode
• an arithmetically encoded data decoding instruction for carrying out an arithmetic-decoding process of arithmetically decoding arithmetically encoded data into a binary signal,
• a matching instruction having a bit map, which represents a matching condition of said arithmetic-decoding process, as an input operand, and
• a branch instruction for making an instruction jump in accordance with a branch condition code;
• an arithmetic-decoding execution section configured to carry out said arithmetic-decoding process by making use of a context number specified by said arithmetically encoded data decoding instruction;
• a history holding section configured to be used to store a history of said binary signals each obtained as a result of said arithmetic-decoding process;
• a matching process section configured to set said branch condition code in accordance with whether or not said history of said binary signal matches said matching condition;
• and
• an instruction control section configured to make said instruction jump in accordance with said branch condition code.