US 2010/0134172 A1Published application

Charge-sharing method and device for clock signal generation

AssigneeAu Optronics Corporation

InventorsChao-Ching Hsu, Mu-Lin Tung, Chung-Shen Cheng

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Abstract

A clock generation circuit has two output ends to provide a first clock signal and a second clock signal, in response to first and second input signals, respectively. A charge storage component is used to transfer some charge from the first output end to the charge storage component when the first clock signal is high for a period of time, and to transfer the charge from the charge storage component to the second output end when the second clock signal is low. At a different period of time in the clock cycle, the charge storage component is used to transfer some charge from the second output end to the charge storage component when the second clock signal is high for a period of time, and to transfer the charge from the charge storage component to the first output end when the first clock signal is low.

Claims25

Dependent claims

A method for generating a first clock signal in a first signal path in response to a first input signal and a second clock signal in a second signal path in response to a second input signal, each of the first and second input signals comprises a first signal state and a second signal state, each of the first and second clock signals comprises a first clock level and a second clock level said method comprising:

performing a first electrical charge transfer from the first signal path to a charge storage component when the first input signal is in the first signal state and the second input signal is in the second signal state, causing the first clock signal to change from the first clock level to a first intermediate level;
causing the first clock signal to operate in the second clock level while the first input level remains in the second signal state;
when the first input signal is in the second signal state and the second input signal is in the first signal state:
causing the second clock signal to change from the second clock level to a second intermediate level;
causing the first clock signal to operate in the second clock level and the second clock signal to operate in the first clock level;
performing a second electrical charge transfer from the second signal path to the charge storage component, causing the second clock signal to change from the first clock level to a third intermediate level;
causing the second clock signal to operate in the second clock state while the second input signal remains in the first signal state;
when the first input signal is in the second signal state and the second input signal is in the first signal state, causing the first clock signal to change from the second clock level to a fourth intermediate level;
and then
when the first input signal is in the first signal state and the second input signal is in the second signal state, causing the first clock signal to change form the fourth intermediate level to the first clock level.

7 more elements

An electronic circuit arranged to receive a first input signal, a second input signal and a control signal for generating a first clock signal in a first signal path in response to the first input signal and a second clock signal in a second signal path in response to the second input signal, each of the first and second input signals comprises a first signal state and a second signal state, each of the first and second clock signals comprises a first clock level and a second clock level said circuit comprising:

a first output end for providing the first clock signal;
a second output end for providing the second clock signal;
a first voltage level shifter for providing in the first signal path a voltage level equal to a first clock level when the first input signal is in the first signal state and providing a voltage level equal to a second clock level when the first input signal is in the second signal state;
a second voltage level shifter for providing in the second signal path a voltage level equal to the first clock level when the second input signal is in the first signal state and providing a voltage level equal to the second clock level when the second input signal is in the second signal state;
a first switching element in the first signal path, the first switching element operable in a connecting state when the first input or in a disconnecting state in response to the first input signal and the control signal;
a second switching element in the second signal path, the second switching element operable in a connecting state or in a disconnecting state in response to the second input signal and the control signal;
a third switching element for electrically connecting a charge storage component to the first signal path at a first connecting point between the first switching element and the first output end, the third switching element is operable in a connecting state and in a disconnecting state in response to the first input signal and the control signal;
and
a fourth switching element for electrically connecting the charge storage component to the second signal path at a second connecting point between the second switching element and the second output end, the fourth switching element is operable in a connecting state and in a disconnecting state in response to the second input signal the control signal.

6 more elements

A clock signal generating circuit, comprising:

a first output for providing a first clock signal in a first signal path;
a second output for providing a second clock signal in a second signal path, each of the first and second outputs operable in a first signal state and a second signal state;
a charge storage component operatively connected to the first and second signal paths;
and
a control module arranged to
perform a first electrical charge transfer from the first signal path to a storage component when the first output is operated in the first state and the second output is operated in the second state;
perform a second electrical charge transfer from the storage component to the second signal path when both the first output and the second output are operated in the second state;
perform third electrical charge transfer from the second signal path to the storage component when the second output is operated in the first state and the first output is operated in the second state;
and
perform fourth electrical charge transfer from the storage component to the second signal path when both the first output and the second output are operated in the second state.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/315,189Filed 28 Nov 2008
Published: 3 Jun 2010
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

G09G 3/3611
Using liquid crystals: control of matrices with row and column drivers
H03K 19/0013
Arrangements for reducing power consumption: in field effect transistor circuits
H03K 19/0016
Arrangements for reducing power consumption: by using a control or a clock signal, e.g. in order to apply power supply
G09G 3/3677
Details of drivers for scan electrodes: suitable for active matrices only