System and method for an accuracy-enhanced dll during a measure initialization mode

A clock generator comprising:

• a multiplexer having an output and first and second inputs, the multiplexer being configured to couple either the first input or the second input to the output responsive to a control signal, the first input coupled to receive an input clock signal;
• a variable delay line having an input coupled to the output of the multiplexer and an output from which a delayed output signal is generated by propagating a signal through the variable delay line from the output of the multiplexer with a variable delay;
• a phase detector having a first input coupled to receive the input clock signal and a second input coupled to receive the delayed output signal from the variable delay line, the phase detector being configured to determine the timing of the input clock signal relative to the timing of the delayed output signal and to adjust the variable delay of the variable delay line in a normal operating mode based on the determined timing;
• and
• a delay measurement circuit coupled to receive the input clock signal and the delayed output signal, the delay measurement circuit being configured to provide a measurement signal to the second input of the multiplexer and to provide the control signal to the multiplexer to couple the input clock signal from first input of the multiplexer to the output of the multiplexer in the normal operating mode and to couple the measurement signal from the second input of the multiplexer to the output of the multiplexer in the delay measurement mode, the delay measurement circuit further configured to measure a delay by allowing the measurement signal to propagate through the adjustable delay circuit and to adjust the variable delay of the variable delay line in the delay measurement mode based on the measured delay.

A memory device, comprising:

• an array of memory cells;
• and
• a clock generator configured to generate an output clock signal responsive to an input clock signal for use by the memory device in reading data from or writing data to the array of memory cells, the clock generator comprising:
• an adjustable delay circuit having an input to which the input clock signal is applied during a normal operation mode, and an output at which the output clock signal is provided by coupling the input clock signal through the adjustable delay circuit, the output clock signal being delayed relative to the input clock signal by an adjustable delay;
• a phase detector having a first input coupled to receive the input clock signal in a normal operation mode and a second input coupled to receive the output clock signal, the phase detector configured to determine the phase difference between the output clock signal and the input clock signal, and to vary the adjustable delay during the normal operation mode but not during a delay measurement mode;
• and
• a delay measurement circuit coupled to receive the inputs clock signal and the outputs clock signal, the delay measurement circuit operable in the delay measurement mode to measure a delay without using the phase detector by coupling a measurement signal to the input of the adjustable delay circuit and allowing the measurement signal to propagate through the adjustable delay circuit, the delay measurement circuit further operable in the delay measurement mode to set the adjustable delay of the adjustable delay circuit according to the measured delay.

A memory device, comprising:

• an array of memory cells;
• and
• a clock generator configured to generate a delayed output signal responsive to an input clock signal for use by the memory device in reading data from or writing data to the array of memory cells, the clock generator comprising:
• a multiplexer having an output and first and second inputs, the multiplexer being configured to couple either the first input or the second input to the output responsive to a control signal, the first input coupled to receive the input clock signal;
• a variable delay line having an input coupled to the output of the multiplexer and an output from which a delayed output signal is generated by propagating a signal through the variable delay line from the output of the multiplexer with a variable delay;
• a phase detector having a first input coupled to receive the input clock signal and a second input coupled to receive the delayed output signal from the variable delay line, the phase detector being configured to determine the timing of the input clock signal relative to the timing of the delayed output signal and to adjust the variable delay of the variable delay line in a normal operating mode based on the determined timing;
• and
• a delay measurement circuit coupled to receive the input clock signal and the delayed output signal, the delay measurement circuit being configured to provide a measurement signal to the second input of the multiplexer and to provide the control signal to the multiplexer to couple the input clock signal from first input of the multiplexer to the output of the multiplexer in the normal operating mode and to couple the measurement signal from the second input of the multiplexer to the output of the multiplexer in the delay measurement mode, the delay measurement circuit further configured to measure a delay by allowing the measurement signal to propagate through the adjustable delay circuit and to adjust the variable delay of the variable delay line in the delay measurement mode based on the measured delay.

A method of generating an output clock signal, comprising:

• receiving an input clock signal;
• in a delay measure mode:
• initializing a measure signal responsive to the input clock signal;
• allowing the measure signal to propagate through a variable delay line;
• comparing the timing of the measure signal after being propagated through the variable delay line with the timing of the input clock signal;
• and
• setting a delay of the variable delay line based on the timing comparison between the timing of the measure signal and the timing of the input clock signal;
• and
• in a normal operating mode:
• propagating the input clock signal through the variable delay line with the delay of the variable delay line set in the delay measurement mode to generate the output clock signal;
• comparing the timing of the output clock signal with the timing of the input clock signal;
• and
• adjusting a delay of the variable delay line based on the timing comparison between the timing of the output clock signal and the timing of the input clock signal.

A method of generating a clock signal comprising:

• receiving an input clock signal and outputting an output clock signal;
• determining a phase difference between the input clock signal and the output clock signal;
• initializing a delay measure mode of operation responsive to a start measure control signal;
• measuring a delay applied to the measure signal relative to the phase difference;
• transitioning to a normal mode of operation responsive to A stop measure control signal;
• and
• applying the measured delay to the received input clock signal to generate the output clock signal with a phase synchronized to the phase of the input clock signal.