Time-to-digital converter and all-digital phase-locked loop

An all-digital phase-locked loop (ADPLL), comprising:

• a digital control oscillator which receives a digital control signal and generates an oscillation frequency;
• a converter which receives a reference frequency, and the oscillation frequency generated by the digital control oscillator, delays the oscillation frequency in phases using a plurality of delay elements which are coupled in series, compares the delayed oscillation frequency with the reference frequency, and outputs a phase error of the oscillation frequency with respect to the reference frequency;
• a phase frequency detector which receives the reference frequency, and a third signal from an intermediate node in the plurality of delay elements, and outputs a phase difference between the reference frequency and the third signal;
• a frequency detector which outputs a frequency error of the oscillation frequency with respect to the reference frequency as a digital signal using an output signal of the phase frequency detector and the oscillation frequency;
• and
• a digital loop filter which provides the digital control oscillator with the digital control signal based on the phase error output by the converter and the frequency error output by the frequency detector.

A time-to-digital converter (TDC), comprising:

• a phase-frequency detector;
• a converter;
• a frequency detector;
• and
• an output device,
• wherein the converter outputs a phase error of a first signal and a second signal;
• outputs a phase difference between the first signal and a third signal;
• and outputs a frequency error of the second signal with respect to the first signal.