Delay locked loop circuit
AssigneeHynix Semiconductor Inc.
InventorsYoung-Jun Ku, Ki-Ho Kim
Life of this patent
Estimating the term…
Abstract
A delay locked loop circuit includes a delay locking block configured to delay an input clock and output the delayed input clock as an internal clock to compensate a skew of an external clock and the internal clock, a pulse generating block configured to sequentially output a plurality of pulse signals that control an operation of the delay locking block and enable one of the plurality of pulse signals in response to a detection signal, wherein the plurality of pulse signals is shifted by being synchronized with the input clock, and a pulse detecting block configured to output the detection signal in case all of the plurality of pulse signals are disabled.
Claims17
A delay locked loop circuit, comprising:
- a delay locking block configured to delay an input clock and output the delayed input clock as an internal clock to compensate a skew of an external clock and the internal clock;
- a pulse generating block configured to sequentially output a plurality of pulse signals that control an operation of the delay locking block and enable one of the plurality of pulse signals in response to a detection signal, wherein the plurality of pulse signals is shifted by being synchronized with the input clock;
- and
- a pulse detecting block configured to output the detection signal in case all of the plurality of pulse signals are disabled.
A delay locked loop circuit, comprising:
- a delay locking block configured to delay an input clock and output the delayed input clock as an internal clock;
- a pulse generating block comprising a shift register and configured to sequentially output a plurality of pulse signals that are shifted in the shift register and control an operation of the delay locking block, wherein a pulse signal of the plurality of pulse signals is enabled in response to a detection signal;
- and
- a pulse detecting block configured to output the detection signal when all of the plurality of pulse signals are disabled.
Dependencies are inferred from the claim text.