PLL circuit and method of cotrolling the same
AssigneeNEC Electronics Corporation
InventorToshitsugu Kawashima
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AssigneeNEC Electronics Corporation
InventorToshitsugu Kawashima
Estimating the term…
A PLL circuit according to an exemplary aspect of the present invention includes: a PFD that detects a phase difference between two clock signals; an LPF that outputs a voltage based on a detection result of the PFD; a VCO that controls a frequency of a VCO output clock output based on the voltage; a frequency divider that divides a frequency of the VCO output clock and outputs an output clock; and an automatic adjustment circuit that adjusts a frequency division ratio of the frequency divider based on the voltage. The automatic adjustment circuit includes a comparison circuit that outputs a control signal for controlling the frequency divider and a control signal for controlling the reference voltage. This circuit configuration makes it possible to control an oscillation frequency of a PLL circuit with accuracy and stability.
A PLL circuit comprising:
A method of controlling a PLL circuit, comprising:
Dependencies are inferred from the claim text.