Power-down mode control apparatus and dll circuit having the same

A DLL circuit, comprising:

• a feedback loop configured to delay a reference clock signal in response to a plurality of sample clock signals to generate a delayed clock signal, a feedback clock signal, and a locking completion signal;
• a first phase detection apparatus configured to determine whether or not a phase difference between the reference clock signal and the feedback clock signal exceeds a predetermined range, thereby generating a first phase detection signal;
• a power-down mode control apparatus configured to determine whether or not to enable first and/or second power-down enter signals in response to the reference clock signal, the first phase detection signal, the locking completion signal, and a power-down mode signal;
• a clock signal driver configured to drive the reference clock signal to generate a driving clock signal when the first power-down enter signal is disabled;
• and
• a clock signal generator configured to generate the plurality of sample clock signals in response to the driving clock signal when the second power-down enter signal is disabled,
• wherein the plurality of sample clock signals include first and second sample clock signals, and
• wherein the feedback loop includes:
• a delay line configured to delay the reference clock signal in response to a delay control signal to generate the delayed clock signal;
• a delay compensation apparatus configured to delay the delayed clock signal for a prescribed time to generate the feedback clock signal;
• a second phase detection apparatus configured to compare the phase of the reference clock signal with the phase of the feedback clock signal, thereby generating a second phase detection signal;
• an operation mode setting apparatus configured to generate the locking completion signal in response to the first sample clock signal and the second phase detection signal;
• and
• a delay control apparatus configured to generate the delay control signal in response to the second sample clock signal, the second phase detection signal, and the locking completion signal.

A DLL circuit, comprising:

• a feedback loop configured to delay a reference clock signal in response to a plurality of sample clock signals to generate a delayed clock signal, a feedback clock signal, and a locking completion signal;
• a first phase detection apparatus configured to determine whether or not a phase difference between the reference clock signal and the feedback clock signal exceeds a predetermined range, thereby generating a first phase detection signal;
• a power-down mode control apparatus configured to determine whether or not to enable first and/or second power-down enter signals in response to the reference clock signal, the first phase detection signal, the locking completion signal, and a power-down mode signal;
• a clock signal driver configured to drive the reference clock signal to generate a driving clock signal when the first power-down enter signal is disabled;
• and
• a clock signal generator configured to generate the plurality of sample clock signals in response to the driving clock signal when the second power-down enter signal is disabled,
• wherein the first phase detection apparatus includes:
• a first detection block configured to detect whether or not the feedback clock signal has a more advanced phase than the phase of the reference clock signal for a first time, thereby generating a first detection signal;
• a second detection block configured to detect whether or not the reference clock signal has a more advanced phase than the phase of the feedback clock signal for a second time, thereby generating a second detection signal;
• and
• a signal combination block configured to combine the first detection signal and the second detection signal to generate the first phase detection signal.