Package-on-package device, semiconductor package and method for manufacturing the same
AssigneeAdvanced Semiconductor Engineering, Inc.
InventorsLin Wang Yu, Cheng Yi Weng
Life of this patent
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Abstract
A semiconductor package includes a substrate, a chip, an interposer and a molding compound. The chip is electrically connected to the upper surface of the substrate. The interposer is disposed on the chip, and electrically connected to the upper surface of the substrate. The interposer includes an embedded component and a plurality of electric contacts, wherein the embedded component is located between the upper and lower surfaces of the interposer, and the electric contacts are located on the upper surface of the interposer. The molding compound seals the chip and covers the upper surface of the substrate and the lower surface of the interposer.
Claims20
A semiconductor package comprising:
- a substrate having an upper surface and a lower surface opposite to the upper surface;
- a chip electrically connected to the upper surface of the substrate;
- an interposer disposed on the chip and electrically connected to the substrate, wherein the interposer has an upper surface and a lower surface, the lower surface is opposite to the upper surface and faces the chip, the interposer comprises an embedded component and a plurality of first electric contacts, the embedded component is located between the upper and lower surfaces of the interposer, and the first electric contacts are located on the upper surface of the interposer;
- and
- a molding compound sealing the chip and covering the upper surface of the substrate and the lower surface of the interposer.
A method for manufacturing a semiconductor package comprising the following steps of:
- providing a substrate, wherein the substrate has an upper surface and a lower surface opposite to the upper surface;
- electrically connecting a chip to the upper surface of the substrate;
- disposing an interposer on the chip and electrically connecting the interposer to the substrate, wherein the interposer has an upper surface and a lower surface, the lower surface is opposite to the upper surface and faces the chip, the interposer comprises an embedded component and a plurality of electric contacts, the embedded component is located between the upper and lower surfaces, and the electric contacts are located on the upper surface of the interposer;
- and
- applying a molding compound on the upper surface of the substrate to seal the chip and cover the lower surface of the interposer.
A stacked package device comprising:
- a bottom package comprising:
- a first substrate having an upper surface and a lower surface opposite to the upper surface;
- a first chip electrically connected to the first substrate;
- an interposer disposed on the first chip and electrically connected to the first substrate, wherein the interposer has an upper surface and a lower surface, the lower surface is opposite to the upper surface and faces the first chip, the interposer comprises an embedded component and a plurality of first electric contacts, the embedded component is located between the upper and lower surfaces, and the first electric contacts are located on the upper surface of the interposer;
- and
- a first molding compound sealing the first chip and covering the upper surface of the first substrate and the lower surface of the interposer;
- and
- a top package stacked on the bottom package and comprising:
- a second substrate having an upper surface and a lower surface, wherein the lower surface is opposite to the upper surface and electrically connecting to the first electric contacts of the interposer;
- a second chip electrically connected to the second substrate;
- and
- a second molding compound sealing the second chip and covering the upper surface of the substrate.
Dependencies are inferred from the claim text.