Top-side Cooled Semiconductor Package with Stacked Interconnection Plates and Method

A top-side cooled semiconductor package with stacked interconnection plates comprising:

• a circuit substrate having a first plurality of terminal leads for external electrical connection;
• at least one semiconductor die whose bottom surface is bonded atop the circuit substrate;
• a first number of elevation-adaptive low thermal and electrical resistance intimate interconnection plates for bonding a top contact area of said at least one semiconductor die and forming a second plurality of terminal leads for external electrical connection while being three dimensionally formed to accommodate for elevation difference there between;
• and
• a second number of low thermal resistance stacked interconnection plates, each stacked and bonded atop a selected number of intimate interconnection plates, for adding effective top-side cooling to the semiconductor package.

A method of packaging a top-side cooled semiconductor package of a semiconductor die interconnected with a plurality of elevation-adaptive intimate interconnection plates and elevation-adaptive stacked interconnection plates, the method comprises:

• a) providing a circuit substrate having a plurality of terminal leads for external electrical connection;
• b) providing the semiconductor die and attaching it atop the circuit substrate;
• c) providing and attaching the plurality of intimate interconnection plates to the top contact areas of said semiconductor die and said circuit substrate for electrical connection between said top contact areas and said terminal leads;
• and
• d) providing and attaching the plurality of stacked interconnection plates atop the selected number of intimate interconnection plates.