Integrated circuit devices including passive device shielding structures and methods of forming the same
AssigneeSamsung Electronics Co., Ltd.
InventorChulho Chung
Life of this patent
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Abstract
Integrated circuit devices include a semiconductor substrate and a flux line generating passive electronic element on the semiconductor substrate. A dummy gate structure is arranged on the semiconductor substrate in a region below the passive electronic element. The dummy gate includes a plurality of segments, each segment including a first longitudinally extending part and a second longitudinally extending part. The second longitudinally extending part extends at an angle from an end of the first longitudinally extending part. Ones of the segments extend at a substantially same angle and are arranged displaced from each other in an adjacent nested relationship.
Claims20
An integrated circuit device comprising:
- a semiconductor substrate;
- a flux line generating passive electronic element on the semiconductor substrate:
- a three dimensional electromagnetic shield disposed around the passive electronic element and between the passive electronic element and the semiconductor substrate, the electromagnetic shield being configured to inhibit penetration into the semiconductor substrate of flux lines emanating from the passive electronic element and to inhibit escape of flux lines emanating from the passive electronic element from a perimeter surrounding the passive electronic element.
A method of forming an integrated circuit device, comprising:
- forming an active device and a passive device region in a semiconductor substrate;
- concurrently forming a gate electrode of an active device in the active device region and a dummy gate electrode in the passive device region;
- forming a first interlayer dielectric layer on the gate electrode and the dummy gate electrode;
- forming a metal plug extending through the first interlayer dielectric layer and contacting the dummy gate electrode at a central region thereof;
- forming a metal layer pattern contacting the metal plug to connect the dummy gate electrode to ground;
- forming a second interlayer dielectric layer on the metal layer pattern;
- and
- forming a flux line generating passive electronic element on the interlayer dielectric layer over the dummy gate electrode.
An integrated circuit device comprising:
- a semiconductor substrate;
- a flux line generating passive electronic element on the semiconductor substrate;
- a dummy gate structure arranged on the semiconductor substrate in a region below the passive electronic element, the dummy gate structure being arranged to inhibit penetration into the semiconductor substrate of flux lines generated by the passive electronic element;
- and
- a metal contact coupled to the dummy gate structure in a central region thereof under the passive electronic element, the metal contact connecting the dummy gate structure to ground.
Dependencies are inferred from the claim text.